Mercurial > flash_v2

annotate packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children 25e238959bae
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1 # ====================================================================
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2 #
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3 # hal_sh_sh4.cdl
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4 #
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5 # SH4 architectural HAL package configuration data
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6 #
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7 # ====================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Red Hat eCos Public License
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12 # Version 1.1 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://www.redhat.com/
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Configurable Operating System,
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22 # released September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Red Hat.
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25 # Portions created by Red Hat are
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26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 # All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 # ====================================================================
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32 ######DESCRIPTIONBEGIN####
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33 #
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34 # Author(s): jskov
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35 # Original data: jskov
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36 # Contributors:
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37 # Date: 1999-10-29
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38 #
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39 #####DESCRIPTIONEND####
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40 #
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41 # ====================================================================
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42
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43 cdl_package CYGPKG_HAL_SH_SH4 {
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44 display "SH4 architecture"
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45 parent CYGPKG_HAL_SH
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46
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47 # Disable for now. Problem with cache consistency
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48 requires ! CYGHWR_HAL_SH_CACHE_ENABLE
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49
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50 hardware
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51 include_dir cyg/hal
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52 define_header hal_sh_sh4.h
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53 description "
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54 The SH4 (SuperH 4) architecture HAL package provides generic
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55 support for this processor architecture. It is also
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56 necessary to select a specific target platform HAL
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57 package."
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58
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59 compile sh4_scif.c var_misc.c variant.S
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60
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61 define_proc {
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62 puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_sh_sh4.h>"
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63 }
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64
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65 # The "-o file" is a workaround for CR100958 - without it the
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66 # output file would end up in the source directory under CygWin.
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67 # n.b. grep does not behave itself under win32
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68 make -priority 1 {
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69 <PREFIX>/include/cyg/hal/sh4_offsets.inc : <PACKAGE>/src/var_mk_defs.c
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70 $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh4_offsets.tmp -o var_mk_defs.tmp -S $<
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71 fgrep .equ var_mk_defs.tmp | sed s/#// > $@
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72 @echo $@ ": \\" > $(notdir $@).deps
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73 @tail +2 sh4_offsets.tmp >> $(notdir $@).deps
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74 @echo >> $(notdir $@).deps
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75 @rm sh4_offsets.tmp var_mk_defs.tmp
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76 }
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77
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78 # CPU variant supported
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79 cdl_component CYGPKG_HAL_SH_7750 {
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80 display "SH 7750 microprocessor"
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81 parent CYGPKG_HAL_SH_CPU
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82 implements CYGINT_HAL_SH_VARIANT
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83 default_value 0
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84 no_define
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85 define -file=system.h CYGPKG_HAL_SH_7750
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86 description "
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87 The SH4 7750 microprocessor. This is an embedded part that in
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88 addition to the SH4 processor core has built in peripherals
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89 such as memory controllers, DMA controllers, serial ports and
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90 timers/counters."
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91 define_proc {
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92 puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7750.h>"
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93 }
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94 }
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95
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96 cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS {
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97 display "SH on-chip generic clock controls"
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98 description "
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99 The various clocks used by the system are controlled by
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100 these options, some of which are derived from platform
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101 settings."
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102 flavor none
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103 no_define
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104
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105 cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 {
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106 display "TMU counter 0 prescaling"
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107 description "
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108 The peripheral clock is driving the counter used for
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109 the real-time clock, prescaled by this factor."
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110 flavor data
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111 legal_values { 4 16 64 256 }
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112 default_value 4
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113 }
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114
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115 cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT {
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116 display "The clock output from PLL1"
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117 no_define
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118 flavor data
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119 calculated { CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_1 }
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120 }
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121
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122 cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED {
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123 display "Processor clock speed (MHz)"
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124 flavor data
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125 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_IFC }
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126 description "
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127 The core (CPU, cache and MMU) speed is computed from
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128 the input clock speed and the IFC divider setting."
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129 }
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130
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131 cdl_option CYGHWR_HAL_SH_BOARD_SPEED {
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132 display "Platform bus clock speed (MHz)"
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133 flavor data
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134 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_BFC }
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135 description "
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136 The bus speed is computed from
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137 the input clock speed and the BFC divider setting."
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138 }
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139
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140 cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED {
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141 display "Processor on-chip peripheral clock speed (MHz)"
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142 flavor data
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143 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_PFC }
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144 description "
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145 The peripheral speed is computed from the input clock
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146 speed and the PFC divider setting."
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147 }
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148 }
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149 }