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annotate packages/compat/uitron/current/tests/testintr.cxx @ 161:ac086aa3217e

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Merge from eCos master repository on 2001-06-08-21:11:51-BST
author jlarmour
date Sun, 10 Jun 2001 19:35:23 +0000
parents afdeb44241de
children e0c0827131d1
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1 //===========================================================================
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2 //
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3 // testintr.c
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4 //
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5 // uITRON "C" test program for ixxx_yyy interrupt safe operators
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6 //
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7 //===========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //===========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): hmt
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35 // Contributors:hmt
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36 // Date: 1998-08-20
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37 // Purpose: uITRON API testing
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38 // Description:
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //===========================================================================
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43
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44 #include <pkgconf/system.h>
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45 #include <pkgconf/uitron.h> // uITRON setup CYGNUM_UITRON_SEMAS
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46 // CYGPKG_UITRON et al
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47 #include <cyg/infra/testcase.h> // testing infrastructure
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48
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49 #ifdef CYGPKG_UITRON // we DO want the uITRON package
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50
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51 #ifdef CYGSEM_KERNEL_SCHED_MLQUEUE // we DO want prioritized threads
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52
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53 #ifdef CYGFUN_KERNEL_THREADS_TIMER // we DO want timout-able calls
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54
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55 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK // we DO want the realtime clock
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56
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57 // we're OK if it's C++ or neither of those two is defined:
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58 #if defined( __cplusplus ) || \
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59 (!defined( CYGIMP_UITRON_INLINE_FUNCS ) && \
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60 !defined( CYGIMP_UITRON_CPP_OUTLINE_FUNCS) )
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61
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62 // =================== TEST CONFIGURATION ===================
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63 #if \
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64 /* test configuration for enough tasks */ \
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65 (CYGNUM_UITRON_TASKS >= 4) && \
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66 (CYGNUM_UITRON_TASKS < 90) && \
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67 (CYGNUM_UITRON_START_TASKS == 1) && \
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68 ( !defined(CYGPKG_UITRON_TASKS_CREATE_DELETE) || \
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69 CYGNUM_UITRON_TASKS_INITIALLY >= 4 ) && \
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70 \
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71 /* the end of the large #if statement */ \
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72 1
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73
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74 // ============================ END ============================
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75
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76 #include <cyg/hal/hal_arch.h>
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77 #include <cyg/hal/hal_intr.h>
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78
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79 #include <cyg/infra/diag.h>
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80
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81 #include <cyg/compat/uitron/uit_func.h> // uITRON
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82 #include <cyg/compat/uitron/uit_ifnc.h> // uITRON interrupt funcs
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83
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84 void set_interrupt_number( void );
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85
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86 unsigned int clock_interrupt = 0;
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87
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88 externC void
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89 cyg_package_start( void )
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90 {
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91 CYG_TEST_INIT();
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92 CYG_TEST_INFO( "Calling cyg_uitron_start()" );
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93 set_interrupt_number();
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94 cyg_uitron_start();
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95 }
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96
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97 extern "C" {
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98 void task1( unsigned int arg );
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99 void task2( unsigned int arg );
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100 void task3( unsigned int arg );
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101 void task4( unsigned int arg );
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102 }
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103
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104 volatile int intercom = 0;
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105 INT scratch = 0;
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106
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107 // Plan: replace (by direct intervention) the ISR and DSR of the regular
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108 // timer interrupt; be sure to ack the clock intr using the appropriate hal
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109 // macros.
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110 //
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111 // The new ISR(s) will simply use the interrupt-safe signalling functions
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112 // to control a 2nd task. Main task will check on the state thereof.
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113 //
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114 // We must test the ixxx_yyy() funcs with the scheduler already locked
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115 // also, by direct sched calls on the KAPI. This must verify that the
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116 // signal only happens when the scheduler unlocks.
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117 //
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118 // The 4 producer ops are:
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119 // iwup_tsk ( ID tskid );
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120 // isig_sem ( ID semid );
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121 // iset_flg ( ID flgid, UINT setptn );
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122 // isnd_msg ( ID mbxid, T_MSG *pk_msg );
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123 //
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124 // and return macros are:
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125 // ret_wup( ID tskid );
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126 // ret_int();
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127 //
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128 // These ISRs perform the producer ops on all available objects in turn.
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129 // Tasks 2-4
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130 // Semas 1-4
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131 // Flags 1-4 with marching bit data; they'll all be set to 0x1ff eventually
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132 // Mboxes 1-4 with an arbitrary pointer
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133
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134 enum {
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135 NOTHING = 0,
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136 SLP,
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137 SEM,
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138 FLG,
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139 MBX,
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140 EXIT
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141 };
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142
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143 #define ACK_CLOCK() CYG_MACRO_START \
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144 HAL_CLOCK_RESET( CYGNUM_HAL_INTERRUPT_RTC, \
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145 CYGNUM_KERNEL_COUNTERS_RTC_PERIOD ); \
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146 HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_RTC ); \
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147 CYG_MACRO_END
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148
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149 #define CHECK_TID() CYG_MACRO_START \
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150 int my_tid; \
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151 ER ercd; \
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152 ercd = get_tid( &my_tid ); \
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153 CYG_TEST_CHECK( E_OK == ercd, "get_tid bad ercd" ); \
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154 CYG_TEST_CHECK( 0 == my_tid, "tid not 0 in ISR" ); \
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155 CYG_MACRO_END
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156
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157
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158 unsigned int
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159 isr_wup_tsk( unsigned int vector, unsigned int data )
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160 {
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161 // Hit TASKS in range 2..4
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162 static int wtid = 2;
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163 ACK_CLOCK();
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164 CHECK_TID();
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165 iwup_tsk( wtid );
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166 wtid++;
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167 if ( 5 == wtid ) wtid = 2;
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168 ret_int();
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169 }
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170
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171 unsigned int
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172 isr_ret_wup( unsigned int vector, unsigned int data )
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173 {
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174 // Hit TASKS in range 2..4
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175 static int rwid = 2;
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176 ACK_CLOCK();
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177 CHECK_TID();
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178 rwid++;
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179 if ( 6 == rwid ) rwid = 3;
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180 ret_wup( rwid - 1 );
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181 }
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182
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183 unsigned int
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184 isr_sig_sem( unsigned int vector, unsigned int data )
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185 {
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186 // Hit SEMAS in range 1..3
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187 static int ssid = 1;
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188 ACK_CLOCK();
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189 CHECK_TID();
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190 isig_sem( ssid );
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191 ssid++;
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192 if ( ssid == 4 ) ssid = 1;
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193 ret_int();
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194 }
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195
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196 unsigned int
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197 isr_set_flg( unsigned int vector, unsigned int data )
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198 {
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199 // Hit FLAGS in range 1..4
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200 static int sfid = 1;
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201 static int sfdata = 0xff;
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202 ACK_CLOCK();
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203 CHECK_TID();
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204 iset_flg( sfid, sfdata );
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205 sfid++;
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206 if ( sfid == 5 ) sfid = 1;
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207 // sfdata <<= 1;
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208 // if ( sfdata == 0x20 ) sfdata = 1; // so that eventually all 0x1f set
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209 ret_int();
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210 }
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211
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212 unsigned int
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213 isr_snd_msg( unsigned int vector, unsigned int data )
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214 {
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215 // Hit MBOXES in range 1..4
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216 static int smid = 1;
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217 ACK_CLOCK();
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218 CHECK_TID();
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219 isnd_msg( smid, (T_MSG *)&smid );
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220 smid++;
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221 if ( smid == 5 ) smid = 1;
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222 ret_int();
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223 }
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224
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225
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226 void attach_isr( unsigned int (*isr)(unsigned int, unsigned int) );
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227 void detach_isr( unsigned int (*isr)(unsigned int, unsigned int) );
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228
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229 void lock_sched( void );
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230 void unlock_sched( void );
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231
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232 volatile int count = -1;
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233
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234 /*
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235 #define BIGDELAY 50000000
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236 #define SMALLDELAY (BIGDELAY/SMALLLOOPS)
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237 #define SMALLLOOPS 3
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238
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239 #define xxxLONGDELAY() \
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240 do { \
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241 int i; \
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242 for ( i = 0; i < BIGDELAY; i++ ) \
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243 if ( wakeups[ 4 ] > prewups[ 4 ] + 99 ) break; \
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244 } while ( 0 )
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245
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246 #define xxxDELAYLOCKSCHED() \
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247 do { \
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248 int i,j; \
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249 for ( j = 0; j < SMALLLOOPS; j++ ) { \
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250 lock_sched(); \
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251 for ( i = 0; i < SMALLDELAY; i++ ) \
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252 if ( wakeups[ 4 ] > prewups[ 4 ] + 99 ) break; \
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253 unlock_sched(); \
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254 if ( wakeups[ 4 ] > prewups[ 4 ] + 99 ) break; \
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255 } \
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256 } while ( 0 )
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257 */
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258
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259 #define SMALLDELAYHW (5000000)
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260 #define EVENTSHW ( 20)
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261 #define SMALLDELAYSIM ( 100000)
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262 #define EVENTSSIM ( 4)
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263
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264 #define SMALLDELAY (smalldelay)
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265 #define EVENTS (events)
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266
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267 static int smalldelay = SMALLDELAYHW;
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268 static int events = EVENTSHW;
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269
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270 #define LONGDELAY() do { \
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271 count = 0; \
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272 do count++; while ( wakeups[ 4 ] < prewups[ 4 ] + EVENTS ); \
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273 } while ( 0 )
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274
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275
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276 #define DELAYLOCKSCHED() \
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277 do { \
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278 count = 0; \
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279 int i; \
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280 do { \
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281 lock_sched(); \
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282 for ( i = 0; i < SMALLDELAY; i++ ) { \
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283 count++; \
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284 if ( wakeups[ 4 ] >= prewups[ 4 ] + EVENTS ) \
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285 break; \
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286 } \
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287 unlock_sched(); \
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288 CYG_TEST_INFO(" [Still iterating, please wait....] "); \
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289 } while ( wakeups[ 4 ] < prewups[ 4 ] + EVENTS ); \
34
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290 } while ( 0 )
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291
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292 #define DELAY() \
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293 if ( 1 & loops ) \
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294 DELAYLOCKSCHED(); \
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295 else \
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296 LONGDELAY();
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297
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298
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299 volatile int wakeups[ 5 ] = { 0,0,0,0,0 };
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300 volatile int prewups[ 5 ] = { 0,0,0,0,0 };
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301
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302
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303 void task1( unsigned int arg )
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304 {
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305 ER ercd;
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306 int loops;
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307
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308 CYG_TEST_INFO( "Task 1 running" );
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309
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310 if ( cyg_test_is_simulator ) {
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311 // take less time
66
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312 events = EVENTSSIM;
34
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313 }
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314
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315
76
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316 // First test that dis_int() and ena_int() work for the clock interrupt
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317 #ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
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318 ercd = ena_int( 123456789 ); // Hope this is large enough to error
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319 CYG_TEST_CHECK( E_PAR == ercd, "ena_int bad ercd !E_PAR" );
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320 ercd = dis_int( 123456789 );
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321 CYG_TEST_CHECK( E_PAR == ercd, "dis_int bad ercd !E_PAR" );
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322 #endif
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323
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324 // This may take too long on a sim...
161
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325 // On the synthetic target this test cannot run reliably - the
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326 // loop counting assumes exclusive access to the processor.
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327 #ifndef CYGPKG_HAL_SYNTH
76
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328 if ( ! cyg_test_is_simulator ) {
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329 SYSTIME t1, t2;
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330
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331 CYG_TEST_INFO( "Testing masking of clock interrupt" );
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332
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333 ercd = get_tim( &t1 );
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334 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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335
78
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336 // Wait for a tick. This loop acts as a synchronizer for the loop
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337 // below, ensuring that it starts just after a tick.
76
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338 for ( loops = 0; loops < 10000000; loops++ ) {
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339 ercd = get_tim( &t2 );
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340 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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341 if ( t2 != t1 )
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342 break;
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343 }
78
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344 // Wait for next tick. Reset loops counter so we get the
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345 // approximate loop count of one clock tick.
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346 for ( loops = 0; loops < 10000000; loops++ ) {
76
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347 ercd = get_tim( &t1 );
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348 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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349 if ( t2 != t1 )
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350 break;
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351 }
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352
78
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353 // save how many loops could be executed in one tick. Multiply
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354 // with 3 : we run loops in pairs below and add the time of
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355 // one extra to avoid small variations to trigger failures.
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356 intercom = loops * 3;
76
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357
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358 ercd = ena_int( clock_interrupt ); // was initialized already
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359 CYG_TEST_CHECK( E_OK == ercd, "ena_int bad ercd" );
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360
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361 ercd = get_tim( &t1 );
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362 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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363
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364 // Wait for a tick
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365 for ( loops = intercom; loops > 0; loops-- ) {
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366 ercd = get_tim( &t2 );
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367 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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368 if ( t2 != t1 )
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369 break;
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370 }
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371 CYG_TEST_CHECK( 0 < loops, "No first tick" );
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372 // and a second one
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373 for ( ; loops > 0; loops-- ) {
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374 ercd = get_tim( &t1 );
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375 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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376 if ( t2 != t1 )
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377 break;
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378 }
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379 CYG_TEST_CHECK( 0 < loops, "No second tick" );
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380
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381 // The PowerPC cannot disable the timer interrupt (separately).
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382 #ifndef CYGPKG_HAL_POWERPC
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383 ercd = dis_int( clock_interrupt ); // was initialized already
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384 CYG_TEST_CHECK( E_OK == ercd, "dis_int bad ercd" );
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385
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386 ercd = get_tim( &t1 );
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387 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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388
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389 // Wait for a tick (should not happen)
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390 for ( loops = intercom; loops > 0; loops-- ) {
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391 ercd = get_tim( &t2 );
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392 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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393 if ( t2 != t1 )
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394 break;
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395 }
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396 CYG_TEST_CHECK( 0 == loops, "A tick occured - should be masked" );
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397 CYG_TEST_CHECK( t1 == t2, "Times are different" );
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398
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399 // Now enable it again and ensure all is well:
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400 ercd = ena_int( clock_interrupt );
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401 CYG_TEST_CHECK( E_OK == ercd, "ena_int bad ercd" );
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402 #endif
161
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403
76
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404 ercd = get_tim( &t1 );
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405 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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406
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407 // Wait for a tick
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408 for ( loops = intercom; loops > 0; loops-- ) {
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409 ercd = get_tim( &t2 );
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410 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
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411 if ( t2 != t1 )
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diff changeset
412 break;
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diff changeset
413 }
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414 CYG_TEST_CHECK( 0 < loops, "No first tick" );
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415 // and a second one
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diff changeset
416 for ( ; loops > 0; loops-- ) {
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417 ercd = get_tim( &t1 );
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418 CYG_TEST_CHECK( E_OK == ercd, "get_tim bad ercd" );
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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diff changeset
419 if ( t2 != t1 )
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diff changeset
420 break;
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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diff changeset
421 }
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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422 CYG_TEST_CHECK( 0 < loops, "No second tick" );
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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diff changeset
423
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424 CYG_TEST_PASS( "dis_int(), ena_int() OK" );
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425 }
161
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426 #endif
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427
34
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428 intercom = 0;
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429
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430 ercd = get_tid( &scratch );
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431 CYG_TEST_CHECK( E_OK == ercd, "get_tid bad ercd" );
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432 CYG_TEST_CHECK( 1 == scratch, "tid not 1" );
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433
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434 // start all other tasks (our prio is 1 by default)
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435 ercd = sta_tsk( 2, 222 );
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436 CYG_TEST_CHECK( E_OK == ercd, "sta_tsk 2 bad ercd" );
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437 ercd = sta_tsk( 3, 333 );
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438 CYG_TEST_CHECK( E_OK == ercd, "sta_tsk 3 bad ercd" );
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439 ercd = sta_tsk( 4, 444 );
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440 CYG_TEST_CHECK( E_OK == ercd, "sta_tsk 4 bad ercd" );
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441 // drop pri of other tasks all to 5
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442 ercd = chg_pri( 2, 5 );
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443 CYG_TEST_CHECK( E_OK == ercd, "chg_pri 2 bad ercd" );
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444 ercd = chg_pri( 3, 5 );
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445 CYG_TEST_CHECK( E_OK == ercd, "chg_pri 3 bad ercd" );
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446 ercd = chg_pri( 4, 5 );
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447 CYG_TEST_CHECK( E_OK == ercd, "chg_pri 4 bad ercd" );
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448
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449 // Test sleep/wakeup
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450 intercom = SLP;
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451 // Drop our prio to lower; they will run in turn until asleep
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452 ercd = chg_pri( 1, 6 );
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453 CYG_TEST_CHECK( E_OK == ercd, "chg_pri 1 (self) bad ercd" );
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454
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455 loops = 4;
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456 do {
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457
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458 if ( 1 & loops )
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459 CYG_TEST_INFO( " (toggling scheduler lock) " );
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460 else
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461 CYG_TEST_INFO( " (unlocked scheduler) " );
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462
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463
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464 CYG_TEST_CHECK( 0 == wakeups[0], "init: Wakeups[0] hit" );
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465 CYG_TEST_CHECK( 0 == wakeups[1], "init: Wakeups[1] hit" );
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466 CYG_TEST_CHECK( prewups[2] == wakeups[2], "init: Wakeups[2] hit" );
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467 CYG_TEST_CHECK( prewups[3] == wakeups[3], "init: Wakeups[3] hit" );
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468 CYG_TEST_CHECK( prewups[4] == wakeups[4], "init: Wakeups[4] hit" );
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469
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470 // -------- TIMERS AND TIMESLICING DISABLED ---------
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471 // install an isr that will wake them all up in turn
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472 attach_isr( isr_wup_tsk );
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473 DELAY();
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474 detach_isr( isr_wup_tsk );
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475 // -------- timers and timeslicing ENABLED ---------
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476
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477 CYG_TEST_CHECK( 0 == wakeups[0], "iwup_tsk: Wakeups[0] hit" );
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478 CYG_TEST_CHECK( 0 == wakeups[1], "iwup_tsk: Wakeups[1] hit" );
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479 CYG_TEST_CHECK( prewups[2] < wakeups[2], "iwup_tsk: Wakeups[2] not hit" );
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480 CYG_TEST_CHECK( prewups[3] < wakeups[3], "iwup_tsk: Wakeups[3] not hit" );
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481 CYG_TEST_CHECK( prewups[4] < wakeups[4], "iwup_tsk: Wakeups[4] not hit" );
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482 diag_printf( "INFO:<(fg loops %10d) thread wakeups : %2d %2d %2d >\n", count,
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483 wakeups[2] - prewups[2],
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484 wakeups[3] - prewups[3],
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485 wakeups[4] - prewups[4] );
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486 prewups[2] = wakeups[2];
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487 prewups[3] = wakeups[3];
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488 prewups[4] = wakeups[4];
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489
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490 // -------- TIMERS AND TIMESLICING DISABLED ---------
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491 // install an isr that will wake them all up in turn
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492 attach_isr( isr_ret_wup );
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493 DELAY();
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494 detach_isr( isr_ret_wup );
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495 // -------- timers and timeslicing ENABLED ---------
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496
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497 CYG_TEST_CHECK( 0 == wakeups[0], "ret_wup: Wakeups[0] hit" );
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498 CYG_TEST_CHECK( 0 == wakeups[1], "ret_wup: Wakeups[1] hit" );
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499 CYG_TEST_CHECK( prewups[2] < wakeups[2], "ret_wup: Wakeups[2] not hit" );
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500 CYG_TEST_CHECK( prewups[3] < wakeups[3], "ret_wup: Wakeups[3] not hit" );
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501 CYG_TEST_CHECK( prewups[4] < wakeups[4], "ret_wup: Wakeups[4] not hit" );
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502 diag_printf( "INFO:<(fg loops %10d) thread ret_wups: %2d %2d %2d >\n", count,
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503 wakeups[2] - prewups[2],
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504 wakeups[3] - prewups[3],
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505 wakeups[4] - prewups[4] );
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506 prewups[2] = wakeups[2];
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507 prewups[3] = wakeups[3];
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508 prewups[4] = wakeups[4];
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509
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510 // move them on to waiting for a semaphore
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511 intercom = SEM;
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512 ercd = wup_tsk( 2 );
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513 CYG_TEST_CHECK( E_OK == ercd, "wup_tsk(2) bad ercd" );
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514 ercd = wup_tsk( 3 );
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515 CYG_TEST_CHECK( E_OK == ercd, "wup_tsk(3) bad ercd" );
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516 ercd = wup_tsk( 4 );
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517 CYG_TEST_CHECK( E_OK == ercd, "wup_tsk(4) bad ercd" );
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diff changeset
518
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diff changeset
519 CYG_TEST_CHECK( 0 == wakeups[0], "wup_tsk: Wakeups[0] hit" );
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520 CYG_TEST_CHECK( 0 == wakeups[1], "wup_tsk: Wakeups[1] hit" );
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521 CYG_TEST_CHECK( prewups[2] + 1 == wakeups[2], "wup_tsk: Wakeups[2] not hit" );
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522 CYG_TEST_CHECK( prewups[3] + 1 == wakeups[3], "wup_tsk: Wakeups[3] not hit" );
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523 CYG_TEST_CHECK( prewups[4] + 1 == wakeups[4], "wup_tsk: Wakeups[4] not hit" );
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diff changeset
524 prewups[2] = wakeups[2];
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525 prewups[3] = wakeups[3];
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diff changeset
526 prewups[4] = wakeups[4];
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diff changeset
527
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528 // -------- TIMERS AND TIMESLICING DISABLED ---------
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diff changeset
529 // install an isr that will wake them all up in turn
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diff changeset
530 attach_isr( isr_sig_sem );
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diff changeset
531 DELAY();
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diff changeset
532 detach_isr( isr_sig_sem );
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533 // -------- timers and timeslicing ENABLED ---------
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diff changeset
534
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diff changeset
535 CYG_TEST_CHECK( 0 == wakeups[0], "isig_sem: Wakeups[0] hit" );
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536 CYG_TEST_CHECK( 0 == wakeups[1], "isig_sem: Wakeups[1] hit" );
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537 CYG_TEST_CHECK( prewups[2] < wakeups[2], "isig_sem: Wakeups[2] not hit" );
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diff changeset
538 CYG_TEST_CHECK( prewups[3] < wakeups[3], "isig_sem: Wakeups[3] not hit" );
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diff changeset
539 CYG_TEST_CHECK( prewups[4] < wakeups[4], "isig_sem: Wakeups[4] not hit" );
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540 diag_printf( "INFO:<(fg loops %10d) semaphore waits: %2d %2d %2d >\n", count,
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jlarmour
parents:
diff changeset
541 wakeups[2] - prewups[2],
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jlarmour
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diff changeset
542 wakeups[3] - prewups[3],
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diff changeset
543 wakeups[4] - prewups[4] );
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jlarmour
parents:
diff changeset
544 prewups[2] = wakeups[2];
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jlarmour
parents:
diff changeset
545 prewups[3] = wakeups[3];
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jlarmour
parents:
diff changeset
546 prewups[4] = wakeups[4];
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jlarmour
parents:
diff changeset
547
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jlarmour
parents:
diff changeset
548 // move them on to waiting for a flag
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jlarmour
parents:
diff changeset
549 intercom = FLG;
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jlarmour
parents:
diff changeset
550 ercd = sig_sem( 1 );
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jlarmour
parents:
diff changeset
551 CYG_TEST_CHECK( E_OK == ercd, "sig_sem(1) bad ercd" );
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jlarmour
parents:
diff changeset
552 ercd = sig_sem( 2 );
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jlarmour
parents:
diff changeset
553 CYG_TEST_CHECK( E_OK == ercd, "sig_sem(2) bad ercd" );
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jlarmour
parents:
diff changeset
554 ercd = sig_sem( 3 );
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jlarmour
parents:
diff changeset
555 CYG_TEST_CHECK( E_OK == ercd, "sig_sem(3) bad ercd" );
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
556
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jlarmour
parents:
diff changeset
557 CYG_TEST_CHECK( 0 == wakeups[0], "sig_sem: Wakeups[0] hit" );
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
558 CYG_TEST_CHECK( 0 == wakeups[1], "sig_sem: Wakeups[1] hit" );
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jlarmour
parents:
diff changeset
559 CYG_TEST_CHECK( prewups[2] + 1 == wakeups[2], "sig_sem: Wakeups[2] not hit" );
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jlarmour
parents:
diff changeset
560 CYG_TEST_CHECK( prewups[3] + 1 == wakeups[3], "sig_sem: Wakeups[3] not hit" );
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jlarmour
parents:
diff changeset
561 CYG_TEST_CHECK( prewups[4] + 1 == wakeups[4], "sig_sem: Wakeups[4] not hit" );
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jlarmour
parents:
diff changeset
562 prewups[2] = wakeups[2];
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jlarmour
parents:
diff changeset
563 prewups[3] = wakeups[3];
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jlarmour
parents:
diff changeset
564 prewups[4] = wakeups[4];
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jlarmour
parents:
diff changeset
565
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jlarmour
parents:
diff changeset
566 // -------- TIMERS AND TIMESLICING DISABLED ---------
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jlarmour
parents:
diff changeset
567 // install an isr that will wake them all up in turn
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jlarmour
parents:
diff changeset
568 attach_isr( isr_set_flg );
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jlarmour
parents:
diff changeset
569 DELAY();
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jlarmour
parents:
diff changeset
570 detach_isr( isr_set_flg );
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jlarmour
parents:
diff changeset
571 // -------- timers and timeslicing ENABLED ---------
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jlarmour
parents:
diff changeset
572
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jlarmour
parents:
diff changeset
573 CYG_TEST_CHECK( 0 == wakeups[0], "iset_flg: Wakeups[0] hit" );
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jlarmour
parents:
diff changeset
574 CYG_TEST_CHECK( 0 == wakeups[1], "iset_flg: Wakeups[1] hit" );
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jlarmour
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diff changeset
575 CYG_TEST_CHECK( prewups[2] < wakeups[2], "iset_flg: Wakeups[2] not hit" );
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parents:
diff changeset
576 CYG_TEST_CHECK( prewups[3] < wakeups[3], "iset_flg: Wakeups[3] not hit" );
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jlarmour
parents:
diff changeset
577 CYG_TEST_CHECK( prewups[4] < wakeups[4], "iset_flg: Wakeups[4] not hit" );
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jlarmour
parents:
diff changeset
578 diag_printf( "INFO:<(fg loops %10d) flag waits/sets: %2d %2d %2d >\n", count,
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jlarmour
parents:
diff changeset
579 wakeups[2] - prewups[2],
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jlarmour
parents:
diff changeset
580 wakeups[3] - prewups[3],
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jlarmour
parents:
diff changeset
581 wakeups[4] - prewups[4] );
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jlarmour
parents:
diff changeset
582 prewups[2] = wakeups[2];
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jlarmour
parents:
diff changeset
583 prewups[3] = wakeups[3];
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jlarmour
parents:
diff changeset
584 prewups[4] = wakeups[4];
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jlarmour
parents:
diff changeset
585
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jlarmour
parents:
diff changeset
586 // move them on to waiting for a message box
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jlarmour
parents:
diff changeset
587 intercom = MBX;
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jlarmour
parents:
diff changeset
588 ercd = set_flg( 2, 0xfff );
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jlarmour
parents:
diff changeset
589 CYG_TEST_CHECK( E_OK == ercd, "set_flg(2) bad ercd" );
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jlarmour
parents:
diff changeset
590 ercd = set_flg( 3, 0xfff );
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jlarmour
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diff changeset
591 CYG_TEST_CHECK( E_OK == ercd, "set_flg(3) bad ercd" );
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jlarmour
parents:
diff changeset
592 ercd = set_flg( 4, 0xfff );
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diff changeset
593 CYG_TEST_CHECK( E_OK == ercd, "set_flg(4) bad ercd" );
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jlarmour
parents:
diff changeset
594
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
595 CYG_TEST_CHECK( 0 == wakeups[0], "set_flg: Wakeups[0] hit" );
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jlarmour
parents:
diff changeset
596 CYG_TEST_CHECK( 0 == wakeups[1], "set_flg: Wakeups[1] hit" );
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diff changeset
597 CYG_TEST_CHECK( prewups[2] + 1 == wakeups[2], "set_flg: Wakeups[2] not hit" );
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diff changeset
598 CYG_TEST_CHECK( prewups[3] + 1 == wakeups[3], "set_flg: Wakeups[3] not hit" );
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jlarmour
parents:
diff changeset
599 CYG_TEST_CHECK( prewups[4] + 1 == wakeups[4], "set_flg: Wakeups[4] not hit" );
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jlarmour
parents:
diff changeset
600 prewups[2] = wakeups[2];
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jlarmour
parents:
diff changeset
601 prewups[3] = wakeups[3];
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
602 prewups[4] = wakeups[4];
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jlarmour
parents:
diff changeset
603
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
604 // -------- TIMERS AND TIMESLICING DISABLED ---------
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jlarmour
parents:
diff changeset
605 // install an isr that will wake them all up in turn
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jlarmour
parents:
diff changeset
606 attach_isr( isr_snd_msg );
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jlarmour
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diff changeset
607 DELAY();
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jlarmour
parents:
diff changeset
608 detach_isr( isr_snd_msg );
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jlarmour
parents:
diff changeset
609 // -------- timers and timeslicing ENABLED ---------
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jlarmour
parents:
diff changeset
610
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jlarmour
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diff changeset
611 CYG_TEST_CHECK( 0 == wakeups[0], "isnd_msg: Wakeups[0] hit" );
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diff changeset
612 CYG_TEST_CHECK( 0 == wakeups[1], "isnd_msg: Wakeups[1] hit" );
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diff changeset
613 CYG_TEST_CHECK( prewups[2] < wakeups[2], "isnd_msg: Wakeups[2] not hit" );
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diff changeset
614 CYG_TEST_CHECK( prewups[3] < wakeups[3], "isnd_msg: Wakeups[3] not hit" );
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diff changeset
615 CYG_TEST_CHECK( prewups[4] < wakeups[4], "isnd_msg: Wakeups[4] not hit" );
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diff changeset
616 diag_printf( "INFO:<(fg loops %10d) message rec'pts: %2d %2d %2d >\n", count,
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jlarmour
parents:
diff changeset
617 wakeups[2] - prewups[2],
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jlarmour
parents:
diff changeset
618 wakeups[3] - prewups[3],
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jlarmour
parents:
diff changeset
619 wakeups[4] - prewups[4] );
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jlarmour
parents:
diff changeset
620 prewups[2] = wakeups[2];
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jlarmour
parents:
diff changeset
621 prewups[3] = wakeups[3];
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jlarmour
parents:
diff changeset
622 prewups[4] = wakeups[4];
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jlarmour
parents:
diff changeset
623
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jlarmour
parents:
diff changeset
624 // move them on to exiting, all done
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jlarmour
parents:
diff changeset
625 if ( 1 == loops )
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jlarmour
parents:
diff changeset
626 // then we are about to exit
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jlarmour
parents:
diff changeset
627 intercom = EXIT;
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jlarmour
parents:
diff changeset
628 else
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jlarmour
parents:
diff changeset
629 intercom = SLP;
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jlarmour
parents:
diff changeset
630 ercd = snd_msg( 2, (T_MSG *)&intercom );
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jlarmour
parents:
diff changeset
631 CYG_TEST_CHECK( E_OK == ercd, "snd_msg(2) bad ercd" );
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jlarmour
parents:
diff changeset
632 ercd = snd_msg( 3, (T_MSG *)&intercom );
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jlarmour
parents:
diff changeset
633 CYG_TEST_CHECK( E_OK == ercd, "snd_msg(3) bad ercd" );
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jlarmour
parents:
diff changeset
634 ercd = snd_msg( 4, (T_MSG *)&intercom );
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jlarmour
parents:
diff changeset
635 CYG_TEST_CHECK( E_OK == ercd, "snd_msg(4) bad ercd" );
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jlarmour
parents:
diff changeset
636
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jlarmour
parents:
diff changeset
637 CYG_TEST_CHECK( 0 == wakeups[0], "snd_msg: Wakeups[0] hit" );
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jlarmour
parents:
diff changeset
638 CYG_TEST_CHECK( 0 == wakeups[1], "snd_msg: Wakeups[1] hit" );
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jlarmour
parents:
diff changeset
639 CYG_TEST_CHECK( prewups[2] + 1 == wakeups[2], "snd_msg: Wakeups[2] not hit" );
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jlarmour
parents:
diff changeset
640 CYG_TEST_CHECK( prewups[3] + 1 == wakeups[3], "snd_msg: Wakeups[3] not hit" );
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jlarmour
parents:
diff changeset
641 CYG_TEST_CHECK( prewups[4] + 1 == wakeups[4], "snd_msg: Wakeups[4] not hit" );
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jlarmour
parents:
diff changeset
642 prewups[2] = wakeups[2];
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jlarmour
parents:
diff changeset
643 prewups[3] = wakeups[3];
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jlarmour
parents:
diff changeset
644 prewups[4] = wakeups[4];
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jlarmour
parents:
diff changeset
645
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jlarmour
parents:
diff changeset
646 CYG_TEST_PASS( "Tested ISR invoked uITRON functions" );
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jlarmour
parents:
diff changeset
647
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jlarmour
parents:
diff changeset
648 } while ( 0 < --loops );
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jlarmour
parents:
diff changeset
649
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jlarmour
parents:
diff changeset
650 CYG_TEST_EXIT( "All done" );
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jlarmour
parents:
diff changeset
651 ext_tsk();
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jlarmour
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diff changeset
652 }
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jlarmour
parents:
diff changeset
653
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jlarmour
parents:
diff changeset
654
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jlarmour
parents:
diff changeset
655 void body( int n )
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jlarmour
parents:
diff changeset
656 {
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jlarmour
parents:
diff changeset
657 unsigned int z;
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jlarmour
parents:
diff changeset
658 ER ercd;
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jlarmour
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diff changeset
659 T_MSG *pk_msg;
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jlarmour
parents:
diff changeset
660
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jlarmour
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diff changeset
661 do {
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jlarmour
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diff changeset
662 switch ( intercom ) {
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jlarmour
parents:
diff changeset
663 case NOTHING:
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jlarmour
parents:
diff changeset
664 ercd = slp_tsk();
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jlarmour
parents:
diff changeset
665 CYG_TEST_CHECK( E_OK == ercd, "slp_tsk (doing nothing)" );
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jlarmour
parents:
diff changeset
666 continue;
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jlarmour
parents:
diff changeset
667 case SLP:
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jlarmour
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diff changeset
668 ercd = slp_tsk();
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jlarmour
parents:
diff changeset
669 CYG_TEST_CHECK( E_OK == ercd, "slp_tsk bad ercd" );
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jlarmour
parents:
diff changeset
670 wakeups[ n ]++;
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jlarmour
parents:
diff changeset
671 break;
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jlarmour
parents:
diff changeset
672 case SEM:
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jlarmour
parents:
diff changeset
673 ercd = wai_sem( n-1 ); // 1..3 for semas
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jlarmour
parents:
diff changeset
674 CYG_TEST_CHECK( E_OK == ercd, "wai_sem bad ercd" );
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jlarmour
parents:
diff changeset
675 wakeups[ n ]++;
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jlarmour
parents:
diff changeset
676 break;
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jlarmour
parents:
diff changeset
677 case FLG:
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jlarmour
parents:
diff changeset
678 ercd = wai_flg( &z, n, (1<<n), TWF_CLR | TWF_ANDW );
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
679 CYG_TEST_CHECK( E_OK == ercd, "wai_flg bad ercd" );
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jlarmour
parents:
diff changeset
680 CYG_TEST_CHECK( z & (1<<n), "Flag bit not set" );
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jlarmour
parents:
diff changeset
681 wakeups[ n ]++;
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jlarmour
parents:
diff changeset
682 break;
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jlarmour
parents:
diff changeset
683 case MBX:
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jlarmour
parents:
diff changeset
684 ercd = rcv_msg( &pk_msg, n );
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jlarmour
parents:
diff changeset
685 CYG_TEST_CHECK( E_OK == ercd, "rcv_msg bad ercd" );
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
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parents:
diff changeset
686 CYG_TEST_CHECK( pk_msg, "rcv_msg NULL msg" );
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jlarmour
parents:
diff changeset
687 wakeups[ n ]++;
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jlarmour
parents:
diff changeset
688 break;
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jlarmour
parents:
diff changeset
689 case EXIT:
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jlarmour
parents:
diff changeset
690 return;
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jlarmour
parents:
diff changeset
691 }
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jlarmour
parents:
diff changeset
692 } while ( 1 );
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jlarmour
parents:
diff changeset
693 }
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jlarmour
parents:
diff changeset
694
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jlarmour
parents:
diff changeset
695 void task2( unsigned int arg )
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jlarmour
parents:
diff changeset
696 {
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jlarmour
parents:
diff changeset
697 ER ercd;
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jlarmour
parents:
diff changeset
698 CYG_TEST_INFO( "Task 2 running" );
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jlarmour
parents:
diff changeset
699 ercd = get_tid( &scratch );
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jlarmour
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diff changeset
700 CYG_TEST_CHECK( E_OK == ercd, "get_tid bad ercd" );
66
bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT
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parents: 64
diff changeset
701 CYG_TEST_CHECK( 2 == scratch, "tid not 2" );
34
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jlarmour
parents:
diff changeset
702 if ( 222 != arg )
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jlarmour
parents:
diff changeset
703 CYG_TEST_FAIL( "Task 2 arg not 222" );
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jlarmour
parents:
diff changeset
704 body(2);
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jlarmour
parents:
diff changeset
705 CYG_TEST_INFO( "Task 2 exiting" );
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jlarmour
parents:
diff changeset
706 ext_tsk();
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jlarmour
parents:
diff changeset
707 CYG_TEST_FAIL( "Task 2 failed to exit" );
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jlarmour
parents:
diff changeset
708 }
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jlarmour
parents:
diff changeset
709
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jlarmour
parents:
diff changeset
710 void task3( unsigned int arg )
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jlarmour
parents:
diff changeset
711 {
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jlarmour
parents:
diff changeset
712 ER ercd;
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jlarmour
parents:
diff changeset
713 CYG_TEST_INFO("Task 3 running");
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jlarmour
parents:
diff changeset
714 ercd = get_tid( &scratch );
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jlarmour
parents:
diff changeset
715 CYG_TEST_CHECK( E_OK == ercd, "get_tid bad ercd" );
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jlarmour
parents:
diff changeset
716 CYG_TEST_CHECK( 3 == scratch, "tid not 3" );
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jlarmour
parents:
diff changeset
717 if ( 333 != arg )
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jlarmour
parents:
diff changeset
718 CYG_TEST_FAIL( "Task 3 arg not 333" );
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jlarmour
parents:
diff changeset
719 body(3);
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jlarmour
parents:
diff changeset
720 CYG_TEST_INFO( "Task 3 exiting" );
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jlarmour
parents:
diff changeset
721 ext_tsk();
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jlarmour
parents:
diff changeset
722 CYG_TEST_FAIL( "Task 3 failed to exit" );
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jlarmour
parents:
diff changeset
723 }
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jlarmour
parents:
diff changeset
724
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jlarmour
parents:
diff changeset
725 void task4( unsigned int arg )
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jlarmour
parents:
diff changeset
726 {
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jlarmour
parents:
diff changeset
727 ER ercd;
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jlarmour
parents:
diff changeset
728 CYG_TEST_INFO("Task 4 running");
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jlarmour
parents:
diff changeset
729 ercd = get_tid( &scratch );
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jlarmour
parents:
diff changeset
730 CYG_TEST_CHECK( E_OK == ercd, "get_tid bad ercd" );
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jlarmour
parents:
diff changeset
731 CYG_TEST_CHECK( 4 == scratch, "tid not 4" );
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jlarmour
parents:
diff changeset
732 if ( 444 != arg )
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jlarmour
parents:
diff changeset
733 CYG_TEST_FAIL( "Task 4 arg not 444" );
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jlarmour
parents:
diff changeset
734 body(4);
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jlarmour
parents:
diff changeset
735 CYG_TEST_INFO( "Task 4 exiting" );
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jlarmour
parents:
diff changeset
736 ext_tsk();
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jlarmour
parents:
diff changeset
737 CYG_TEST_FAIL( "Task 4 failed to exit" );
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jlarmour
parents:
diff changeset
738 }
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jlarmour
parents:
diff changeset
739
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jlarmour
parents:
diff changeset
740 // ------------------------------------------------------------------------
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jlarmour
parents:
diff changeset
741 // Start of C++ aware portion, so to speak.
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jlarmour
parents:
diff changeset
742 //
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jlarmour
parents:
diff changeset
743
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jlarmour
parents:
diff changeset
744 #include <cyg/hal/hal_intr.h>
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jlarmour
parents:
diff changeset
745 #include <cyg/kernel/intr.hxx>
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jlarmour
parents:
diff changeset
746 #include <cyg/kernel/clock.hxx>
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jlarmour
parents:
diff changeset
747 #include <cyg/kernel/sched.hxx>
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jlarmour
parents:
diff changeset
748 #include <cyg/kernel/sched.inl>
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jlarmour
parents:
diff changeset
749
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
750 void set_interrupt_number( void )
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
751 {
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
752 clock_interrupt = CYGNUM_HAL_INTERRUPT_RTC;
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
753 }
34
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jlarmour
parents:
diff changeset
754
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jlarmour
parents:
diff changeset
755 // This snippet stolen from kernel/.../clock.cxx to be able to detach
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jlarmour
parents:
diff changeset
756 // the RTC from its interrupt source.
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jlarmour
parents:
diff changeset
757 class Cyg_RealTimeClock
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jlarmour
parents:
diff changeset
758 : public Cyg_Clock
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jlarmour
parents:
diff changeset
759 {
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jlarmour
parents:
diff changeset
760 public:
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jlarmour
parents:
diff changeset
761 Cyg_Interrupt interrupt;
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jlarmour
parents:
diff changeset
762
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jlarmour
parents:
diff changeset
763 static cyg_uint32 isr(cyg_vector vector, CYG_ADDRWORD data);
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jlarmour
parents:
diff changeset
764
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jlarmour
parents:
diff changeset
765 static void dsr(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data);
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jlarmour
parents:
diff changeset
766
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jlarmour
parents:
diff changeset
767 Cyg_RealTimeClock();
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jlarmour
parents:
diff changeset
768 };
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jlarmour
parents:
diff changeset
769
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jlarmour
parents:
diff changeset
770
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jlarmour
parents:
diff changeset
771 static Cyg_Interrupt uit_intr(
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jlarmour
parents:
diff changeset
772 (unsigned)CYGNUM_HAL_INTERRUPT_RTC, // Vector to attach to
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jlarmour
parents:
diff changeset
773 0, // Queue priority
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jlarmour
parents:
diff changeset
774 (unsigned)0, // Data pointer
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jlarmour
parents:
diff changeset
775 &isr_wup_tsk, // Interrupt Service Routine
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jlarmour
parents:
diff changeset
776 &cyg_uitron_dsr // Deferred Service Routine
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jlarmour
parents:
diff changeset
777 );
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jlarmour
parents:
diff changeset
778
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
779 void
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
780 attach_isr( unsigned int (*isr)(unsigned int, unsigned int) )
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
781 {
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jlarmour
parents:
diff changeset
782 int inuse;
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jlarmour
parents:
diff changeset
783 int old_ints;
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jlarmour
parents:
diff changeset
784 Cyg_RealTimeClock *prtc = (Cyg_RealTimeClock *)Cyg_Clock::real_time_clock;
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jlarmour
parents:
diff changeset
785 HAL_INTERRUPT_MASK( CYGNUM_HAL_INTERRUPT_RTC );
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jlarmour
parents:
diff changeset
786 HAL_DISABLE_INTERRUPTS(old_ints);
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jlarmour
parents:
diff changeset
787 prtc->interrupt.detach();
88
afdeb44241de Merge from eCos master repository on 2000-05-12-07:47:04-BST
jlarmour
parents: 84
diff changeset
788 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN
afdeb44241de Merge from eCos master repository on 2000-05-12-07:47:04-BST
jlarmour
parents: 84
diff changeset
789 // Only check that the vector was cleared when there's a specific
afdeb44241de Merge from eCos master repository on 2000-05-12-07:47:04-BST
jlarmour
parents: 84
diff changeset
790 // vector for the RTC. In chain mode, other interrupt handlers
afdeb44241de Merge from eCos master repository on 2000-05-12-07:47:04-BST
jlarmour
parents: 84
diff changeset
791 // may prevent the shared vector from being cleared when detaching
afdeb44241de Merge from eCos master repository on 2000-05-12-07:47:04-BST
jlarmour
parents: 84
diff changeset
792 // the RTC ISR, and this assertion fails.
34
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
793 HAL_INTERRUPT_IN_USE( CYGNUM_HAL_INTERRUPT_RTC, inuse );
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jlarmour
parents:
diff changeset
794 CYG_TEST_CHECK( !inuse, "Failed to detach clock ISR" );
88
afdeb44241de Merge from eCos master repository on 2000-05-12-07:47:04-BST
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parents: 84
diff changeset
795 #endif
34
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jlarmour
parents:
diff changeset
796 uit_intr = Cyg_Interrupt(
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jlarmour
parents:
diff changeset
797 CYGNUM_HAL_INTERRUPT_RTC, // Vector to attach to
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jlarmour
parents:
diff changeset
798 1, // Queue priority
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jlarmour
parents:
diff changeset
799 0, // Data pointer
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
800 isr, // Interrupt Service Routine
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jlarmour
parents:
diff changeset
801 cyg_uitron_dsr // Deferred Service Routine
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
802 );
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jlarmour
parents:
diff changeset
803 uit_intr.attach();
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jlarmour
parents:
diff changeset
804 HAL_INTERRUPT_IN_USE( CYGNUM_HAL_INTERRUPT_RTC, inuse );
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jlarmour
parents:
diff changeset
805 CYG_TEST_CHECK( inuse, "Failed to attach new ISR" );
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jlarmour
parents:
diff changeset
806 ACK_CLOCK();
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jlarmour
parents:
diff changeset
807 HAL_RESTORE_INTERRUPTS(old_ints);
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jlarmour
parents:
diff changeset
808 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC );
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
809 }
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jlarmour
parents:
diff changeset
810
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
811 void
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jlarmour
parents:
diff changeset
812 detach_isr( unsigned int (*isr)(unsigned int, unsigned int) )
29bc183297e1 Merge from eCos master repository on 1999-09-02-16:26:10-BST
jlarmour
parents:
diff changeset
813 {
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jlarmour
parents:
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814 int inuse;
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815 int old_ints;
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816 Cyg_RealTimeClock *prtc = (Cyg_RealTimeClock *)Cyg_Clock::real_time_clock;
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817 HAL_INTERRUPT_MASK( CYGNUM_HAL_INTERRUPT_RTC );
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818 HAL_DISABLE_INTERRUPTS(old_ints);
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819 uit_intr.detach();
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820 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN
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821 // See comment above in attach_isr.
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822 HAL_INTERRUPT_IN_USE( CYGNUM_HAL_INTERRUPT_RTC, inuse );
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823 CYG_TEST_CHECK( !inuse, "Failed to detach my ISR" );
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824 #endif
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825 prtc->interrupt.attach();
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826 HAL_INTERRUPT_IN_USE( CYGNUM_HAL_INTERRUPT_RTC, inuse );
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827 CYG_TEST_CHECK( inuse, "Failed to attach clock ISR" );
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828 ACK_CLOCK();
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829 HAL_RESTORE_INTERRUPTS(old_ints);
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830 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC );
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831 }
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832
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833
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834 void
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835 lock_sched( void )
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836 {
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837 cyg_uint32 l;
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838 Cyg_Scheduler::lock();
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839 l = Cyg_Scheduler::get_sched_lock();
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840 CYG_TEST_CHECK( 0 < l, "lock: Sched not locked" );
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841 CYG_TEST_CHECK( 2 > l, "lock: Sched already locked" );
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842 }
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843
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844 void
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845 unlock_sched( void )
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846 {
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847 cyg_uint32 l;
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848 l = Cyg_Scheduler::get_sched_lock();
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849 CYG_TEST_CHECK( 0 < l, "unlock: Sched not locked" );
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850 CYG_TEST_CHECK( 2 > l, "unlock: Sched already locked" );
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851 Cyg_Scheduler::unlock();
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852 }
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853
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854
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855 #else // not enough (or too many) uITRON objects configured in
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856 #define N_A_MSG "not enough uITRON objects to run test"
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857 #endif // not enough (or too many) uITRON objects configured in
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858 #else // not C++ and some C++ specific options enabled
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859 #define N_A_MSG "C++ specific options selected but this is C"
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860 #endif // not C++ and some C++ specific options enabled
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861 #else // ! CYGVAR_KERNEL_COUNTERS_CLOCK - can't test without it
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862 #define N_A_MSG "no CYGVAR_KERNEL_COUNTERS_CLOCK"
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863 #endif // ! CYGVAR_KERNEL_COUNTERS_CLOCK - can't test without it
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864 #else // ! CYGFUN_KERNEL_THREADS_TIMER - can't test without it
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865 #define N_A_MSG "no CYGFUN_KERNEL_THREADS_TIMER"
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866 #endif // ! CYGFUN_KERNEL_THREADS_TIMER - can't test without it
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867 #else // ! CYGIMP_THREAD_PRIORITY - can't test without it
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868 #define N_A_MSG "no CYGSEM_KERNEL_SCHED_MLQUEUE"
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869 #endif // ! CYGSEM_KERNEL_SCHED_MLQUEUE - can't test without it
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870 #else // ! CYGPKG_UITRON
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871 #define N_A_MSG "uITRON Compatibility layer disabled"
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872 #endif // CYGPKG_UITRON
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873
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874 #ifdef N_A_MSG
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875 externC void
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876 cyg_start( void )
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877 {
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878 CYG_TEST_INIT();
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879 CYG_TEST_NA( N_A_MSG );
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880 }
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881 #endif // N_A_MSG defined ie. we are N/A.
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882
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883 // EOF testintr.c