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annotate packages/hal/sparclite/sim/current/include/hal_cache.h @ 66:bf00f99aec69 ecos-sw-2000-02-02
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
| author | jlarmour |
|---|---|
| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
| children | e0c0827131d1 |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL Cache control support (such as it is in the simulator) | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Red Hat eCos Public License |
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15 // Version 1.1 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://www.redhat.com/ |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Configurable Operating System, |
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25 // released September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Red Hat. |
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28 // Portions created by Red Hat are |
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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30 // All Rights Reserved. |
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31 // ------------------------------------------- |
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32 // |
| 2 | 33 //####COPYRIGHTEND#### |
| 34 //============================================================================= | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 37 // Author(s): nickg, gthomas, hmt | |
| 38 // Contributors: nickg, gthomas, hmt | |
| 39 // Date: 1999-01-28 | |
| 40 // Purpose: Define Interrupt support | |
| 41 // Description: The macros defined here provide the HAL APIs for handling | |
| 42 // the caches. | |
| 43 // | |
| 44 // Usage: | |
| 45 // #include <cyg/hal/hal_cache.h> | |
| 46 // ... | |
| 47 // | |
| 48 // | |
| 49 //####DESCRIPTIONEND#### | |
| 50 // | |
| 51 //============================================================================= | |
| 52 | |
| 53 #include <pkgconf/hal.h> | |
| 54 #include <pkgconf/hal_sparclite.h> | |
| 55 | |
| 56 #include <cyg/infra/cyg_type.h> | |
| 57 | |
| 58 //----------------------------------------------------------------------------- | |
| 59 // SPARClite cache macros | |
| 60 | |
| 61 //----------------------------------------------------------------------------- | |
| 62 // Cache dimensions | |
| 63 | |
| 64 // Data cache | |
| 65 #define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes | |
| 66 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line | |
| 67 #define HAL_DCACHE_WAYS 4 // Associativity of the cache | |
| 68 | |
| 69 // Instruction cache | |
| 70 #define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes | |
| 71 #define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line | |
| 72 #define HAL_ICACHE_WAYS 4 // Associativity of the cache | |
| 73 | |
| 74 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 75 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 76 | |
| 77 //----------------------------------------------------------------------------- | |
| 78 // Global control of data cache | |
| 79 | |
| 80 // Enable the data cache | |
| 81 #define HAL_DCACHE_ENABLE() | |
| 82 // Disable the data cache | |
| 83 #define HAL_DCACHE_DISABLE() | |
| 84 // Invalidate the entire cache | |
| 85 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 86 // Synchronize the contents of the cache with memory. | |
| 87 #define HAL_DCACHE_SYNC() | |
| 88 | |
| 89 // Set the data cache refill burst size | |
| 90 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 91 | |
| 92 // Set the data cache write mode | |
| 93 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 94 | |
| 95 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 96 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 97 | |
| 98 // Load the contents of the given address range into the data cache | |
| 99 // and then lock the cache so that it stays there. | |
| 100 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 101 | |
| 102 // Undo a previous lock operation | |
| 103 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 104 | |
| 105 // Unlock entire cache | |
| 106 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 107 | |
| 108 //----------------------------------------------------------------------------- | |
| 109 // Data cache line control | |
| 110 | |
| 111 // Allocate cache lines for the given address range without reading its | |
| 112 // contents from memory. | |
| 113 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 114 | |
| 115 // Write dirty cache lines to memory and invalidate the cache entries | |
| 116 // for the given address range. | |
| 117 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 118 | |
| 119 // Invalidate cache lines in the given range without writing to memory. | |
| 120 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 121 | |
| 122 // Write dirty cache lines to memory for the given address range. | |
| 123 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 124 | |
| 125 // Preread the given range into the cache with the intention of reading | |
| 126 // from it later. | |
| 127 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 128 | |
| 129 // Preread the given range into the cache with the intention of writing | |
| 130 // to it later. | |
| 131 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 132 | |
| 133 // Allocate and zero the cache lines associated with the given range. | |
| 134 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 135 | |
| 136 //----------------------------------------------------------------------------- | |
| 137 // Global control of Instruction cache - use Data cache controls since they | |
| 138 // are not separatable. | |
| 139 | |
| 140 // Enable the instruction cache | |
| 141 #define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() | |
| 142 | |
| 143 // Disable the instruction cache | |
| 144 #define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() | |
| 145 | |
| 146 // Invalidate the entire cache | |
| 147 #define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL() | |
| 148 | |
| 149 // Synchronize the contents of the cache with memory. | |
| 150 #define HAL_ICACHE_SYNC() | |
| 151 | |
| 152 // Set the instruction cache refill burst size | |
| 153 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 154 | |
| 155 // Load the contents of the given address range into the instruction cache | |
| 156 // and then lock the cache so that it stays there. | |
| 157 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 158 | |
| 159 // Undo a previous lock operation | |
| 160 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 161 | |
| 162 // Unlock entire cache | |
| 163 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 164 | |
| 165 //----------------------------------------------------------------------------- | |
| 166 // Instruction cache line control | |
| 167 | |
| 168 // Invalidate cache lines in the given range without writing to memory. | |
| 169 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 170 | |
| 171 //----------------------------------------------------------------------------- | |
| 172 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 173 // End of hal_cache.h |