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annotate packages/compat/uitron/current/include/uit_ifnc.inl @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 29bc183297e1
children bf00f99aec69
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1 #ifndef CYGONCE_COMPAT_UITRON_UIT_IFNC_INL
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2 #define CYGONCE_COMPAT_UITRON_UIT_IFNC_INL
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3 //===========================================================================
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4 //
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5 // uit_ifnc.inl
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6 //
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7 // uITRON compatibility functions
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8 //
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9 //===========================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.0 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://sourceware.cygnus.com/ecos
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17 //
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18 // Software distributed under the License is distributed on an
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //===========================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): hmt
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37 // Contributors: hmt
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38 // Date: 1999-08-16
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39 // Purpose: uITRON compatibility functions
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40 // Description:
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41 //
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42 //####DESCRIPTIONEND####
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43 //
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44 //===========================================================================
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45
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46 #ifdef CYGPKG_UITRON
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47
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48 #ifdef CYGPRI_UITRON_FUNCS_HERE_AND_NOW
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49
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50 class Cyg_Uit_Action {
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51 public:
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52 typedef enum {
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53 WUP_TSK,
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54 SIG_SEM,
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55 SET_FLG,
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56 SND_MSG
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57 } action;
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58 };
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59
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60 extern volatile int cyg_uit_dsr_actions_head;
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61 extern volatile int cyg_uit_dsr_actions_tail;
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62
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63 #define CYGNUM_UITRON_ISR_ACTION_QUEUEMASK (CYGNUM_UITRON_ISR_ACTION_QUEUESIZE-1)
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64
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65 #if ((~CYGNUM_UITRON_ISR_ACTION_QUEUEMASK) & \
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66 ~((~CYGNUM_UITRON_ISR_ACTION_QUEUEMASK)-1)) \
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67 != CYGNUM_UITRON_ISR_ACTION_QUEUESIZE
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68 #error CYGNUM_UITRON_ISR_ACTION_QUEUESIZE not a power of 2
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69 #endif
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70
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71 extern Cyg_Uit_Action::action
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72 cyg_uit_dsr_actions[ CYGNUM_UITRON_ISR_ACTION_QUEUESIZE ];
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73
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74 extern ID
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75 cyg_uit_dsr_act_ids[ CYGNUM_UITRON_ISR_ACTION_QUEUESIZE ];
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76
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77 extern CYG_ADDRWORD
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78 cyg_uit_dsr_act_a1s[ CYGNUM_UITRON_ISR_ACTION_QUEUESIZE ];
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79
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80 CYG_UIT_FUNC_INLINE
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81 ER
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82 iwup_tsk ( ID tskid )
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83 {
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84 #ifdef CYGSEM_UITRON_ISRFUNCS_TRY_IMMEDIATE_EXECUTION
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85 if ( 1 >= Cyg_Scheduler::get_sched_lock() ) {
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86 // then this ISR is the first one, and the sched was locked by the
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87 // interrupt code. So this is safe.
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88 return wup_tsk( tskid );
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89 }
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90 #endif
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91
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92 register int i, head;
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93 i = cyg_uit_dsr_actions_head;
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94 head = CYGNUM_UITRON_ISR_ACTION_QUEUEMASK & ( 1 + i );
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95 // If interrupts can be recursive, then there is a race here where a
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96 // slot may be overwritten by a recursive interrupt, or actions from
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97 // such lost; better though than having a slot contain *mixed* data
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98 // from two intermingled interrupts.
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99 if ( head != cyg_uit_dsr_actions_tail ) {
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100 cyg_uit_dsr_actions_head = head;
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101 cyg_uit_dsr_actions[ i ] = Cyg_Uit_Action::WUP_TSK;
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102 cyg_uit_dsr_act_ids[ i ] = tskid;
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103 }
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104 return E_OK;
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105 }
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106
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107 #ifdef CYGPKG_UITRON_SEMAS
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108 #if 0 < CYG_UITRON_NUM( SEMAS )
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109 CYG_UIT_FUNC_INLINE
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110 ER
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111 isig_sem ( ID semid )
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112 {
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113 #ifdef CYGSEM_UITRON_ISRFUNCS_TRY_IMMEDIATE_EXECUTION
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114 if ( 1 >= Cyg_Scheduler::get_sched_lock() ) {
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115 // then this ISR is the first one, and the sched was locked by the
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116 // interrupt code. So this is safe.
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117 return sig_sem( semid );
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118 }
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119 #endif
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120
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121 register int i, head;
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122 i = cyg_uit_dsr_actions_head;
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123 head = CYGNUM_UITRON_ISR_ACTION_QUEUEMASK & ( 1 + i );
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124 // If interrupts can be recursive, then there is a race here where a
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125 // slot may be overwritten by a recursive interrupt, or actions from
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126 // such lost; better though than having a slot contain *mixed* data
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127 // from two intermingled interrupts.
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128 if ( head != cyg_uit_dsr_actions_tail ) {
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129 cyg_uit_dsr_actions_head = head;
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130 cyg_uit_dsr_actions[ i ] = Cyg_Uit_Action::SIG_SEM;
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131 cyg_uit_dsr_act_ids[ i ] = semid;
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132 }
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133 return E_OK;
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134 }
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135 #endif // 0 < CYG_UITRON_NUM( SEMAS )
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136 #endif // CYGPKG_UITRON_SEMAS
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137
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138 #ifdef CYGPKG_UITRON_FLAGS
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139 #if 0 < CYG_UITRON_NUM( FLAGS )
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140 CYG_UIT_FUNC_INLINE
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141 ER
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142 iset_flg ( ID flgid, UINT setptn )
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143 {
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144 #ifdef CYGSEM_UITRON_ISRFUNCS_TRY_IMMEDIATE_EXECUTION
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145 if ( 1 >= Cyg_Scheduler::get_sched_lock() ) {
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146 // then this ISR is the first one, and the sched was locked by the
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147 // interrupt code. So this is safe.
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148 return set_flg( flgid, setptn );
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149 }
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150 #endif
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151
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152 register int i, head;
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153 i = cyg_uit_dsr_actions_head;
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154 head = CYGNUM_UITRON_ISR_ACTION_QUEUEMASK & ( 1 + i );
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155 // If interrupts can be recursive, then there is a race here where a
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156 // slot may be overwritten by a recursive interrupt, or actions from
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157 // such lost; better though than having a slot contain *mixed* data
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158 // from two intermingled interrupts.
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159 if ( head != cyg_uit_dsr_actions_tail ) {
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160 cyg_uit_dsr_actions_head = head;
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161 cyg_uit_dsr_actions[ i ] = Cyg_Uit_Action::SET_FLG;
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162 cyg_uit_dsr_act_ids[ i ] = flgid;
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163 cyg_uit_dsr_act_a1s[ i ] = (CYG_ADDRWORD)setptn;
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164 }
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165 return E_OK;
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166 }
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167 #endif // 0 < CYG_UITRON_NUM( FLAGS )
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168 #endif // CYGPKG_UITRON_FLAGS
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169
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170 #ifdef CYGPKG_UITRON_MBOXES
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171 #if 0 < CYG_UITRON_NUM( MBOXES )
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172 CYG_UIT_FUNC_INLINE
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173 ER
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174 isnd_msg ( ID mbxid, T_MSG *pk_msg )
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175 {
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176 #ifdef CYGSEM_UITRON_ISRFUNCS_TRY_IMMEDIATE_EXECUTION
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177 if ( 1 >= Cyg_Scheduler::get_sched_lock() ) {
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178 // then this ISR is the first one, and the sched was locked by the
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179 // interrupt code. So this is safe.
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180 return snd_msg( mbxid, pk_msg );
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181 }
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182 #endif
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183
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184 register int i, head;
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185 i = cyg_uit_dsr_actions_head;
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186 head = CYGNUM_UITRON_ISR_ACTION_QUEUEMASK & ( 1 + i );
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187 // If interrupts can be recursive, then there is a race here where a
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188 // slot may be overwritten by a recursive interrupt, or actions from
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189 // such lost; better though than having a slot contain *mixed* data
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190 // from two intermingled interrupts.
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191 if ( head != cyg_uit_dsr_actions_tail ) {
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192 cyg_uit_dsr_actions_head = head;
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193 cyg_uit_dsr_actions[ i ] = Cyg_Uit_Action::SND_MSG;
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194 cyg_uit_dsr_act_ids[ i ] = mbxid;
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195 cyg_uit_dsr_act_a1s[ i ] = (CYG_ADDRWORD)pk_msg;
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196 }
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197 return E_OK;
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198 }
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199 #endif // 0 < CYG_UITRON_NUM( MBOXES )
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200 #endif // CYGPKG_UITRON_MBOXES
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201
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202 // ========================================================================
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203
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204 #endif // CYGPKG_UITRON
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205
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206 #endif // CYGPRI_UITRON_FUNCS_HERE_AND_NOW
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207
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208 #endif // CYGONCE_COMPAT_UITRON_UIT_IFNC_INL
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209 //EOF uit_ifnc.inl