Mercurial > flash_v2
annotate packages/hal/mips/arch/current/src/mips-stub.c @ 64:c38311975d4f ecos-sw-2000-01-28
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
| author | jlarmour |
|---|---|
| date | Fri, 28 Jan 2000 04:59:39 +0000 |
| parents | a0774359f013 |
| children | bf00f99aec69 |
| rev | line source |
|---|---|
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1 //======================================================================== |
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2 // |
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3 // mips-stub.h |
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4 // |
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5 // Helper functions for stub, generic to all MIPS processors |
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6 // |
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7 //======================================================================== |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
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30 //####COPYRIGHTEND#### |
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31 //======================================================================== |
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32 //#####DESCRIPTIONBEGIN#### |
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33 // |
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34 // Author(s): Red Hat, nickg |
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35 // Contributors: Red Hat, nickg |
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36 // Date: 1998-06-08 |
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37 // Purpose: |
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38 // Description: Helper functions for stub, generic to all MIPS processors |
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39 // Usage: |
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40 // |
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41 //####DESCRIPTIONEND#### |
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42 // |
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43 //======================================================================== |
| 0 | 44 |
| 45 #include <stddef.h> | |
| 46 | |
| 2 | 47 #include <pkgconf/hal.h> |
| 0 | 48 |
| 49 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 50 | |
| 2 | 51 #include <cyg/hal/hal_stub.h> |
| 0 | 52 |
| 2 | 53 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
| 54 #include <cyg/hal/mips-regs.h> | |
| 0 | 55 |
| 2 | 56 #include <cyg/hal/hal_arch.h> |
| 57 #include <cyg/hal/mips_opcode.h> | |
| 0 | 58 |
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59 typedef unsigned long t_inst; |
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60 |
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61 /*---------------------------------------------------------------------- |
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62 * Asynchronous interrupt support |
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63 */ |
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64 |
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65 static struct |
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66 { |
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67 t_inst *targetAddr; |
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68 t_inst savedInstr; |
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69 } asyncBuffer; |
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70 |
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71 /* Called to asynchronously interrupt a running program. |
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72 Must be passed address of instruction interrupted. |
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73 This is typically called in response to a debug port |
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74 receive interrupt. |
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75 */ |
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76 |
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77 void |
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78 install_async_breakpoint(void *epc) |
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79 { |
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80 long gp_save; |
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81 |
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82 /* This may be called from a separately linked program, |
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83 so we need to save and restore the incoming gp register |
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84 and setup our stub local gp register. |
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85 Alternatively, we could skip this foolishness if we |
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86 compiled libstub with "-G 0". */ |
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87 |
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88 __asm__ volatile ( "move %0,$28\n" |
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89 ".extern _gp\n" |
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90 "la $28,_gp\n" |
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91 : "=r" (gp_save) ); |
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92 |
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93 asyncBuffer.targetAddr = epc; |
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94 asyncBuffer.savedInstr = *(t_inst *)epc; |
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95 *(t_inst *)epc = *(t_inst *)_breakinst; |
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96 __instruction_cache(CACHE_FLUSH); |
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97 __data_cache(CACHE_FLUSH); |
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98 |
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99 __asm__ volatile ( "move $28,%0\n" :: "r"(gp_save) ); |
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100 } |
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101 |
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102 /*--------------------------------------------------------------------*/ |
| 0 | 103 /* Given a trap value TRAP, return the corresponding signal. */ |
| 104 | |
| 105 int __computeSignal (unsigned int trap_number) | |
| 106 { | |
| 107 switch (trap_number) | |
| 108 { | |
| 109 case EXC_INT: | |
| 110 /* External interrupt */ | |
| 111 return SIGINT; | |
| 112 | |
| 113 case EXC_RI: | |
| 114 /* Reserved instruction */ | |
| 115 case EXC_CPU: | |
| 116 /* Coprocessor unusable */ | |
| 117 return SIGILL; | |
| 118 | |
| 119 case EXC_BP: | |
| 120 /* Break point */ | |
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121 if (asyncBuffer.targetAddr != NULL) |
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122 { |
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123 /* BP installed by serial driver to stop running program */ |
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124 *asyncBuffer.targetAddr = asyncBuffer.savedInstr; |
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125 __instruction_cache(CACHE_FLUSH); |
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126 __data_cache(CACHE_FLUSH); |
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127 asyncBuffer.targetAddr = NULL; |
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128 return SIGINT; |
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129 } |
| 0 | 130 return SIGTRAP; |
| 131 | |
| 132 case EXC_OVF: | |
| 133 /* Arithmetic overflow */ | |
| 134 case EXC_TRAP: | |
| 135 /* Trap exception */ | |
| 136 case EXC_FPE: | |
| 137 /* Floating Point Exception */ | |
| 138 return SIGFPE; | |
| 139 | |
| 140 case EXC_IBE: | |
| 141 /* Bus error (Ifetch) */ | |
| 142 case EXC_DBE: | |
| 143 /* Bus error (data load or store) */ | |
| 144 return SIGBUS; | |
| 145 | |
| 146 case EXC_MOD: | |
| 147 /* TLB modification exception */ | |
| 148 case EXC_TLBL: | |
| 149 /* TLB miss (Load or Ifetch) */ | |
| 150 case EXC_TLBS: | |
| 151 /* TLB miss (Store) */ | |
| 152 case EXC_ADEL: | |
| 153 /* Address error (Load or Ifetch) */ | |
| 154 case EXC_ADES: | |
| 155 /* Address error (Store) */ | |
| 156 return SIGSEGV; | |
| 157 | |
| 158 case EXC_SYS: | |
| 159 /* System call */ | |
| 160 return SIGSYS; | |
| 161 | |
| 162 default: | |
| 163 return SIGTERM; | |
| 164 } | |
| 165 } | |
| 166 | |
| 167 /* Return the trap number corresponding to the last-taken trap. */ | |
| 168 | |
| 169 int __get_trap_number (void) | |
| 170 { | |
| 171 return (get_register (CAUSE) & CAUSE_EXCMASK) >> CAUSE_EXCSHIFT; | |
| 172 } | |
| 173 | |
| 174 /* Set the currently-saved pc register value to PC. This also updates NPC | |
| 175 as needed. */ | |
| 176 | |
| 177 void set_pc (target_register_t pc) | |
| 178 { | |
| 179 put_register (PC, pc); | |
| 180 } | |
| 181 | |
| 182 | |
| 183 /*---------------------------------------------------------------------- | |
| 184 * Single-step support | |
| 185 */ | |
| 186 | |
| 187 /* Saved instruction data for single step support. */ | |
| 188 | |
| 189 static struct | |
| 190 { | |
| 191 t_inst *targetAddr; | |
| 192 t_inst savedInstr; | |
| 193 } instrBuffer; | |
| 194 | |
| 195 | |
| 196 /* Set things up so that the next user resume will execute one instruction. | |
| 197 This may be done by setting breakpoints or setting a single step flag | |
| 198 in the saved user registers, for example. */ | |
| 199 | |
| 2 | 200 void __single_step (void) |
| 0 | 201 { |
| 202 InstFmt inst; | |
| 203 t_inst *pc = (t_inst *) get_register (PC); | |
| 204 | |
| 2 | 205 instrBuffer.targetAddr = pc + 1; /* set default */ |
| 0 | 206 |
| 2 | 207 inst.word = *pc; /* read the next instruction */ |
| 0 | 208 |
| 209 //diag_printf("pc %08x %08x\n",pc,inst.word); | |
| 210 | |
| 211 switch (inst.RType.op) { /* override default if branch */ | |
| 212 case OP_SPECIAL: | |
| 213 switch (inst.RType.func) { | |
| 214 case OP_JR: | |
| 215 case OP_JALR: | |
| 216 instrBuffer.targetAddr = (t_inst *) get_register (inst.RType.rs); | |
| 217 break; | |
| 218 }; | |
| 219 break; | |
| 220 | |
| 221 case OP_REGIMM: | |
| 222 switch (inst.IType.rt) { | |
| 223 case OP_BLTZ: | |
| 224 case OP_BLTZL: | |
| 225 case OP_BLTZAL: | |
| 226 case OP_BLTZALL: | |
|
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227 if ((int)get_register (inst.IType.rs) < 0 ) |
| 0 | 228 instrBuffer.targetAddr = |
| 229 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 230 + (get_register (PC) + 4)); | |
| 231 else | |
| 232 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 233 break; | |
| 234 case OP_BGEZ: | |
| 235 case OP_BGEZL: | |
| 236 case OP_BGEZAL: | |
| 237 case OP_BGEZALL: | |
|
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238 if ((int)get_register (inst.IType.rs) >= 0 ) |
| 0 | 239 instrBuffer.targetAddr = |
| 240 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 241 + (get_register (PC) + 4)); | |
| 242 else | |
| 243 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 244 break; | |
| 245 }; | |
| 246 break; | |
| 247 | |
| 248 case OP_J: | |
| 249 case OP_JAL: | |
| 250 instrBuffer.targetAddr = | |
| 251 (t_inst *)((inst.JType.target<<2) | |
| 2 | 252 + ((get_register (PC) + 4)&0xf0000000)); |
| 0 | 253 break; |
| 254 | |
| 255 case OP_BEQ: | |
| 256 case OP_BEQL: | |
| 257 if (get_register (inst.IType.rs) == get_register (inst.IType.rt)) | |
| 258 instrBuffer.targetAddr = | |
| 259 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 2 | 260 + (get_register (PC) + 4)); |
| 0 | 261 else |
| 262 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 263 break; | |
| 264 case OP_BNE: | |
| 265 case OP_BNEL: | |
| 266 if (get_register (inst.IType.rs) != get_register (inst.IType.rt)) | |
| 267 instrBuffer.targetAddr = | |
| 268 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 2 | 269 + (get_register (PC) + 4)); |
| 0 | 270 else |
| 271 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 272 break; | |
| 273 case OP_BLEZ: | |
| 274 case OP_BLEZL: | |
|
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275 if ((int)get_register (inst.IType.rs) <= 0) |
| 0 | 276 instrBuffer.targetAddr = |
| 277 (t_inst *)(((signed short)inst.IType.imm<<2) + (get_register (PC) + 4)); | |
| 278 else | |
| 279 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 280 break; | |
| 281 case OP_BGTZ: | |
| 282 case OP_BGTZL: | |
|
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283 if ((int)get_register (inst.IType.rs) > 0) |
| 0 | 284 instrBuffer.targetAddr = |
| 285 (t_inst *)(((signed short)inst.IType.imm<<2) + (get_register (PC) + 4)); | |
| 286 else | |
| 287 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 288 break; | |
| 289 | |
|
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290 #ifdef CYGHWR_HAL_MIPS_FPU |
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291 |
| 0 | 292 case OP_COP1: |
| 293 if (inst.RType.rs == OP_BC) | |
| 294 switch (inst.RType.rt) { | |
| 295 case COPz_BCF: | |
| 296 case COPz_BCFL: | |
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297 if (get_register (FCR31) & FCR31_C) |
| 0 | 298 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); |
| 299 else | |
| 300 instrBuffer.targetAddr = | |
| 301 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 302 + (get_register (PC) + 4)); | |
| 303 break; | |
| 304 case COPz_BCT: | |
| 305 case COPz_BCTL: | |
|
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306 if (get_register (FCR31) & FCR31_C) |
| 0 | 307 instrBuffer.targetAddr = |
| 308 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 309 + (get_register (PC) + 4)); | |
| 310 else | |
| 311 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 312 break; | |
| 313 }; | |
| 314 break; | |
| 315 #endif | |
| 316 | |
| 317 } | |
| 318 } | |
| 319 | |
| 320 | |
| 321 /* Clear the single-step state. */ | |
| 322 | |
| 2 | 323 void __clear_single_step (void) |
| 0 | 324 { |
| 325 //diag_printf("clear_ss ta %08x\n",instrBuffer.targetAddr); | |
| 326 if (instrBuffer.targetAddr != NULL) | |
| 327 { | |
| 328 *instrBuffer.targetAddr = instrBuffer.savedInstr; | |
| 329 instrBuffer.targetAddr = NULL; | |
| 330 } | |
| 331 instrBuffer.savedInstr = NOP_INSTR; | |
| 332 } | |
| 333 | |
| 334 | |
| 2 | 335 void __install_breakpoints () |
| 0 | 336 { |
| 337 //diag_printf("install_bpt ta %08x\n",instrBuffer.targetAddr); | |
| 338 if (instrBuffer.targetAddr != NULL) | |
| 339 { | |
| 340 instrBuffer.savedInstr = *instrBuffer.targetAddr; | |
| 341 *instrBuffer.targetAddr = __break_opcode (); | |
| 342 //diag_printf("ta %08x si %08x *ta %08x\n", | |
| 343 // instrBuffer.targetAddr,instrBuffer.savedInstr,*instrBuffer.targetAddr); | |
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344 |
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345 /* Ensure that the planted breakpoint makes it out to memory and |
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346 is subsequently loaded into the instruction cache. |
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347 */ |
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348 __data_cache (CACHE_FLUSH) ; |
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349 __instruction_cache (CACHE_FLUSH) ; |
| 0 | 350 } |
| 351 } | |
| 352 | |
| 2 | 353 void __clear_breakpoints (void) |
| 354 { | |
| 355 } | |
| 356 | |
| 0 | 357 |
| 358 /* If the breakpoint we hit is in the breakpoint() instruction, return a | |
| 359 non-zero value. */ | |
| 360 | |
| 361 int | |
| 362 __is_breakpoint_function () | |
| 363 { | |
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364 return get_register (PC) == (target_register_t)(unsigned long)&CYG_LABEL_NAME(breakinst); |
| 0 | 365 } |
| 366 | |
| 367 | |
| 368 /* Skip the current instruction. Since this is only called by the | |
| 369 stub when the PC points to a breakpoint or trap instruction, | |
| 370 we can safely just skip 4. */ | |
| 371 | |
| 372 void __skipinst (void) | |
| 373 { | |
| 2 | 374 put_register (PC, get_register (PC) + 4); |
| 0 | 375 } |
| 376 | |
| 377 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
