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annotate packages/hal/powerpc/mpc8xx/current/include/var_cache.h @ 70:c5536bad4c24 ecos-sw-2000-02-11

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Merge from eCos master repository on 2000-02-11-15:46:40-GMT
author jlarmour
date Fri, 11 Feb 2000 16:47:32 +0000
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children e0c0827131d1
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //=============================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): nickg
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37 // Contributors:nickg, jskov
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38 // Date: 2000-04-02
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39 // Purpose: Variant cache control API
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40 // Description: The macros defined here provide the HAL APIs for handling
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41 // cache control operations on the MPC8xx variant CPUs.
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42 // Usage: Is included via the architecture cache header:
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43 // #include <cyg/hal/hal_cache.h>
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44 // ...
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <pkgconf/hal.h>
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51 #include <cyg/infra/cyg_type.h>
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52
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53 #include <cyg/hal/ppc_regs.h>
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54
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55 #include <cyg/hal/plf_cache.h>
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56
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57
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58 //-----------------------------------------------------------------------------
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59 // Cache dimensions - these vary between the 8xx sub-models
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60
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61 #if defined(CYGPKG_HAL_POWERPC_MPC860)
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62 // Data cache
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63 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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64 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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65 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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66
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67 // Instruction cache
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68 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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69 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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70 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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71 #endif // defined(CYGPKG_HAL_POWERPC_MPC860)
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72
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73 #if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
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74 // Data cache
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75 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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76 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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77 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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78
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79 // Instruction cache
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80 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes
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81 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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82 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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83 #endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
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84
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85 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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86 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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87
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88 //-----------------------------------------------------------------------------
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89 // Global control of data cache
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90
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91 // Enable the data cache
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92 #define HAL_DCACHE_ENABLE() \
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93 asm volatile ("sync;" \
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94 "mtspr %0, %1;" \
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95 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))
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96
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97 // Disable the data cache
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98 #define HAL_DCACHE_DISABLE() \
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99 asm volatile ("sync;" \
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100 "mtspr %0, %1;" \
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101 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))
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102
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103 // Invalidate the entire cache
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104 // Note: Any locked lines will not be invalidated.
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105 #define HAL_DCACHE_INVALIDATE_ALL() \
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106 asm volatile ("sync;" \
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107 "mtspr %0, %1;" \
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108 : : "I" (CYGARC_REG_DC_CST), \
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109 "r" (CYGARC_REG_DC_CMD_IA))
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110
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111 // Synchronize the contents of the cache with memory.
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112 #define HAL_DCACHE_SYNC() \
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113 CYG_MACRO_START \
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114 cyg_int32 i; \
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115 for (i = 0; i < HAL_DCACHE_SETS; i++){ \
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116 asm volatile ("sync;" \
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117 "mtspr %0, %2;" \
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118 "mtspr %1, %4;" \
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119 "mtspr %0, %3;" \
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120 "mtspr %1, %4;" \
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121 : /* no output */ \
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122 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \
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123 /* %1 */ "I" (CYGARC_REG_DC_CST), \
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124 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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125 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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126 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \
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127 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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128 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \
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129 } \
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130 CYG_MACRO_END
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131
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132 // Query the state of the data cache
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133 #define HAL_DCACHE_IS_ENABLED(_state_) \
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134 asm volatile ("mfspr %0, %1;" \
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135 "rlwinm %0,%0,1,31,31;" \
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136 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST))
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137
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138 // Set the data cache refill burst size
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139 //#define HAL_DCACHE_BURST_SIZE(_size_)
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140
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141 // Set the data cache write mode
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142 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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143
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144 //#define HAL_DCACHE_WRITETHRU_MODE 0
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145 //#define HAL_DCACHE_WRITEBACK_MODE 1
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146
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147
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148 // Load the contents of the given address range into the data cache
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149 // and then lock the cache so that it stays there.
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150
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151 // Restrictions: This implementation only allows a single area to be
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152 // locked at any one time. This area must be 2kB or less in size.
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153
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154 // Implementation: Flush entire cache, then invalidate it. This
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155 // ensures that the fetched data go into way0.
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156
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157 #define HAL_DCACHE_LOCK(_base_, _size_) \
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158 CYG_MACRO_START \
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159 cyg_int32 __scratch; \
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160 cyg_uint32 __base = (cyg_uint32)(_base_); \
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161 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \
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162 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \
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163 HAL_DCACHE_DISABLE(); \
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164 HAL_DCACHE_SYNC (); \
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165 HAL_DCACHE_INVALIDATE_ALL (); \
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166 HAL_DCACHE_ENABLE(); \
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167 do { \
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168 asm volatile ("lbz %0,0(%1);" \
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169 "sync;" \
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170 "mtspr %2, %4;" \
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171 "mtspr %3, %5;" \
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172 : /* %0 */ "=&r" (__scratch) \
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173 : /* %1 */ "b" (__base), \
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174 /* %2 */ "I" (CYGARC_REG_DC_ADR), \
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175 /* %3 */ "I" (CYGARC_REG_DC_CST), \
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176 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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177 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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178 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \
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179 __l++; \
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180 __base += HAL_DCACHE_LINE_SIZE; \
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181 } while (__count--); \
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182 CYG_MACRO_END
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183
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184
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185 // Undo a previous lock operation
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186
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187 // Implementation: Unlocks entire cache.
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188
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189 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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190 HAL_DCACHE_UNLOCK_ALL()
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191
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192
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193 // Unlock entire cache
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194 #define HAL_DCACHE_UNLOCK_ALL() \
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195 CYG_MACRO_START \
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196 asm volatile ("sync;" \
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197 "mtspr %0, %1;" \
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198 : : "I" (CYGARC_REG_DC_CST), \
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199 "r" (CYGARC_REG_DC_CMD_UA)); \
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200 CYG_MACRO_END
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201
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202
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203
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204 //-----------------------------------------------------------------------------
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205 // Data cache line control
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206
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207 // Allocate cache lines for the given address range without reading its
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208 // contents from memory.
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209 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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210
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211 // Write dirty cache lines to memory and invalidate the cache entries
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212 // for the given address range.
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213 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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214 CYG_MACRO_START \
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215 cyg_uint32 __base = (cyg_uint32) (_base_); \
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216 cyg_int32 __size = (cyg_int32) (_size_); \
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217 while (__size > 0) { \
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218 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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219 __base += HAL_DCACHE_LINE_SIZE; \
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220 __size -= HAL_DCACHE_LINE_SIZE; \
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221 } \
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222 CYG_MACRO_END
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223
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224 // Invalidate cache lines in the given range without writing to memory.
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225 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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226 CYG_MACRO_START \
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227 cyg_uint32 __base = (cyg_uint32) (_base_); \
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228 cyg_int32 __size = (cyg_int32) (_size_); \
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229 while (__size > 0) { \
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230 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
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231 __base += HAL_DCACHE_LINE_SIZE; \
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232 __size -= HAL_DCACHE_LINE_SIZE; \
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233 } \
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234 CYG_MACRO_END
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235
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236 // Write dirty cache lines to memory for the given address range.
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237 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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238 CYG_MACRO_START \
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239 cyg_uint32 __base = (cyg_uint32) (_base_); \
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240 cyg_int32 __size = (cyg_int32) (_size_); \
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241 while (__size > 0) { \
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242 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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243 __base += HAL_DCACHE_LINE_SIZE; \
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244 __size -= HAL_DCACHE_LINE_SIZE; \
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245 } \
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246 CYG_MACRO_END
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247
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248 // Preread the given range into the cache with the intention of reading
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249 // from it later.
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250 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
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251 CYG_MACRO_START \
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252 cyg_uint32 __base = (cyg_uint32) (_base_); \
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253 cyg_int32 __size = (cyg_int32) (_size_); \
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254 while (__size > 0) { \
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255 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
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256 __base += HAL_DCACHE_LINE_SIZE; \
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257 __size -= HAL_DCACHE_LINE_SIZE; \
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258 } \
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259 CYG_MACRO_END
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260
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261 // Preread the given range into the cache with the intention of writing
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262 // to it later.
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263 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
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264 CYG_MACRO_START \
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265 cyg_uint32 __base = (cyg_uint32) (_base_); \
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266 cyg_int32 __size = (cyg_int32) (_size_); \
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267 while (__size > 0) { \
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268 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
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269 __base += HAL_DCACHE_LINE_SIZE; \
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270 __size -= HAL_DCACHE_LINE_SIZE; \
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271 } \
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272 CYG_MACRO_END
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273
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274 // Allocate and zero the cache lines associated with the given range.
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275 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
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276 CYG_MACRO_START \
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277 cyg_uint32 __base = (cyg_uint32) (_base_); \
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278 cyg_int32 __size = (cyg_int32) (_size_); \
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279 while (__size > 0) { \
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280 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
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281 __base += HAL_DCACHE_LINE_SIZE; \
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282 __size -= HAL_DCACHE_LINE_SIZE; \
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283 } \
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284 CYG_MACRO_END
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285
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286 //-----------------------------------------------------------------------------
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287 // Global control of Instruction cache
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288
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289 // Enable the instruction cache
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290 #define HAL_ICACHE_ENABLE() \
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291 asm volatile ("isync;" \
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292 "mtspr %0, %1;" \
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293 "isync" \
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294 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
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295
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296 // Disable the instruction cache
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297 #define HAL_ICACHE_DISABLE() \
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298 asm volatile ("isync;" \
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299 "mtspr %0, %1;" \
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300 "isync" \
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301 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD))
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302
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303 // Invalidate the entire cache
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304 #define HAL_ICACHE_INVALIDATE_ALL() \
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305 asm volatile ("isync;" \
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306 "mtspr %0, %1;" \
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307 "isync" \
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308 : : "I" (CYGARC_REG_IC_CST), \
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309 "r" (CYGARC_REG_IC_CMD_IA))
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310
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311 // Synchronize the contents of the cache with memory.
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312 #define HAL_ICACHE_SYNC() \
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313 HAL_ICACHE_INVALIDATE_ALL()
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314
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315 // Query the state of the instruction cache
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316 #define HAL_ICACHE_IS_ENABLED(_state_) \
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317 asm volatile ("mfspr %0, %1;" \
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318 "rlwinm %0,%0,1,31,31;" \
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319 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST))
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320
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321 // Set the instruction cache refill burst size
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322 //#define HAL_ICACHE_BURST_SIZE(_size_)
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323
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324
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325 // Load the contents of the given address range into the instruction cache
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326 // and then lock the cache so that it stays there.
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327
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328 // Restrictions: This implementation only allows a single area to be
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329 // locked at any one time. This area must be 2kB or less in size.
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330
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331 // Implementation: Flush entire cache, then invalidate it. This
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332 // ensures that the fetched data go into way0.
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333
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334 #define HAL_ICACHE_LOCK(_base_, _size_) \
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335 CYG_MACRO_START \
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336 unsigned long __base = \
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337 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \
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338 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \
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339 do { \
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340 asm volatile ("mtspr %0, %2;" \
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341 "mtspr %1, %3;" \
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342 "isync;" \
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343 : /* no output */ \
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344 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \
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345 /* %1 */ "I" (CYGARC_REG_IC_CST), \
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346 /* %2 */ "r" (__base), \
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347 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \
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348 __base += HAL_ICACHE_LINE_SIZE; \
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349 } while (__count--); \
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350 CYG_MACRO_END
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351
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352 // Undo a previous lock operation
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353
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354 // Implementation: Unlocks entire cache.
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355 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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356 HAL_ICACHE_UNLOCK_ALL()
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357
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358 // Unlock entire cache
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359 #define HAL_ICACHE_UNLOCK_ALL() \
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360 CYG_MACRO_START \
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361 asm volatile ("sync;" \
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362 "mtspr %0, %1;" \
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363 : : "I" (CYGARC_REG_IC_CST), \
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364 "r" (CYGARC_REG_IC_CMD_UA)); \
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365 CYG_MACRO_END
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366
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367 //-----------------------------------------------------------------------------
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368 // Instruction cache line control
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369
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370 // Invalidate cache lines in the given range without writing to memory.
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371 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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372
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373 //-----------------------------------------------------------------------------
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374 #endif // ifndef CYGONCE_VAR_CACHE_H
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375 // End of var_cache.h