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1 //========================================================================== |
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2 // |
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3 // adder_eth.c |
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4 // |
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5 // Ethernet device driver specifics for Analogue & Micro Adder (PPC850) |
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6 // |
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7 //========================================================================== |
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8 //####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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12 // Copyright (C) 2002 Gary Thomas |
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13 // |
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14 // eCos is free software; you can redistribute it and/or modify it under |
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15 // the terms of the GNU General Public License as published by the Free |
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16 // Software Foundation; either version 2 or (at your option) any later version. |
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17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
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22 // |
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23 // You should have received a copy of the GNU General Public License along |
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24 // with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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26 // |
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27 // As a special exception, if other files instantiate templates or use macros |
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28 // or inline functions from this file, or you compile this file and link it |
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29 // with other works to produce a work based on this file, this file does not |
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30 // by itself cause the resulting work to be covered by the GNU General Public |
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31 // License. However the source code for this file must still be made available |
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32 // in accordance with section (3) of the GNU General Public License. |
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33 // |
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34 // This exception does not invalidate any other reasons why a work based on |
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35 // this file might be covered by the GNU General Public License. |
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36 // |
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37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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38 // at http://sources.redhat.com/ecos/ecos-license/ |
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39 // ------------------------------------------- |
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40 //####ECOSGPLCOPYRIGHTEND#### |
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41 //####BSDCOPYRIGHTBEGIN#### |
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42 // |
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43 // ------------------------------------------- |
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44 // |
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45 // Portions of this software may have been derived from OpenBSD or other sources, |
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46 // and are covered by the appropriate copyright disclaimers included herein. |
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47 // |
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48 // ------------------------------------------- |
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49 // |
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50 //####BSDCOPYRIGHTEND#### |
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51 //========================================================================== |
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52 //#####DESCRIPTIONBEGIN#### |
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53 // |
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54 // Author(s): gthomas |
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55 // Contributors: gthomas |
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56 // Date: 2002-11-25 |
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57 // Purpose: |
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58 // Description: platform driver specifics for A&M Adder |
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59 // |
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60 // |
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61 //####DESCRIPTIONEND#### |
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62 // |
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63 //========================================================================== |
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64 |
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65 // Ethernet device driver support for PHY on Adder/MPC850 |
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66 |
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67 #include <pkgconf/system.h> |
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68 #include <cyg/infra/cyg_type.h> |
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69 #include <cyg/infra/diag.h> |
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70 |
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71 #include <cyg/hal/hal_arch.h> |
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72 #include <cyg/hal/hal_cache.h> |
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73 #include <cyg/hal/hal_if.h> |
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74 #include <cyg/hal/drv_api.h> |
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75 |
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76 #include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics |
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77 #include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions |
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78 |
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79 // MII interface |
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80 #define MII_Start 0x40000000 |
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81 #define MII_Read 0x20000000 |
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82 #define MII_Write 0x10000000 |
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83 #define MII_Cmd 0x30000000 |
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84 #define MII_Phy(phy) (phy << 23) |
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85 #define MII_Reg(reg) (reg << 18) |
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86 #define MII_TA 0x00020000 |
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87 |
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88 // Transceiver mode |
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89 #define PHY_BMCR 0x00 // Register number |
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90 #define PHY_BMCR_RESET 0x8000 |
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91 #define PHY_BMCR_LOOPBACK 0x4000 |
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92 #define PHY_BMCR_100MB 0x2000 |
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93 #define PHY_BMCR_AUTO_NEG 0x1000 |
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94 #define PHY_BMCR_POWER_DOWN 0x0800 |
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95 #define PHY_BMCR_ISOLATE 0x0400 |
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96 #define PHY_BMCR_RESTART 0x0200 |
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97 #define PHY_BMCR_FULL_DUPLEX 0x0100 |
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98 #define PHY_BMCR_COLL_TEST 0x0080 |
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99 |
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100 #define PHY_BMSR 0x01 // Status register |
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101 #define PHY_BMSR_AUTO_NEG 0x0020 |
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102 #define PHY_BMSR_LINK 0x0004 |
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103 |
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104 // Bits in port D - used for 2 wire MII interface |
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105 #define MII_DATA 0x1000 |
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106 #define MII_CLOCK 0x0800 |
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107 |
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108 #define MII_SET_DATA(val) \ |
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109 if (val) { \ |
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110 eppc->pio_pddat |= MII_DATA; \ |
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111 } else { \ |
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112 eppc->pio_pddat &= ~MII_DATA; \ |
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113 } |
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114 |
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115 #define MII_GET_DATA() \ |
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116 ((eppc->pio_pddat & MII_DATA) != 0) |
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117 |
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118 #define MII_SET_CLOCK(val) \ |
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119 if (val) { \ |
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120 eppc->pio_pddat |= MII_CLOCK; \ |
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121 } else { \ |
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122 eppc->pio_pddat &= ~MII_CLOCK; \ |
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123 } |
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124 |
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125 static cyg_uint32 |
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126 phy_cmd(cyg_uint32 cmd) |
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127 { |
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128 volatile EPPC *eppc = (volatile EPPC *)eppc_base(); |
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129 cyg_uint32 retval; |
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130 int i, off; |
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131 bool is_read = ((cmd & MII_Cmd) == MII_Read); |
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132 |
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133 // Set both bits as output |
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134 eppc->pio_pddir |= MII_DATA | MII_CLOCK; |
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135 |
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136 // Preamble |
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137 for (i = 0; i < 32; i++) { |
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138 MII_SET_CLOCK(0); |
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139 MII_SET_DATA(1); |
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140 CYGACC_CALL_IF_DELAY_US(1); |
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141 MII_SET_CLOCK(1); |
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142 CYGACC_CALL_IF_DELAY_US(1); |
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143 } |
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144 |
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145 // Command/data |
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146 for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) { |
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147 MII_SET_CLOCK(0); |
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148 MII_SET_DATA((cmd >> off) & 0x00000001); |
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149 CYGACC_CALL_IF_DELAY_US(1); |
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150 MII_SET_CLOCK(1); |
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151 CYGACC_CALL_IF_DELAY_US(1); |
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152 } |
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153 |
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154 retval = cmd; |
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155 |
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156 // If read, fetch data register |
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157 if (is_read) { |
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158 retval >>= 16; |
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159 |
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160 MII_SET_CLOCK(0); |
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161 eppc->pio_pddir &= ~MII_DATA; // Data bit is now input |
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162 CYGACC_CALL_IF_DELAY_US(1); |
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163 MII_SET_CLOCK(1); |
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164 CYGACC_CALL_IF_DELAY_US(1); |
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165 MII_SET_CLOCK(0); |
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166 CYGACC_CALL_IF_DELAY_US(1); |
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167 |
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168 for (i = 0, off = 15; i < 16; i++, off--) { |
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169 MII_SET_CLOCK(1); |
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170 retval <<= 1; |
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171 retval |= MII_GET_DATA(); |
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172 CYGACC_CALL_IF_DELAY_US(1); |
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173 MII_SET_CLOCK(0); |
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174 CYGACC_CALL_IF_DELAY_US(1); |
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175 } |
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176 } |
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177 |
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178 // Set both bits as output |
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179 eppc->pio_pddir |= MII_DATA | MII_CLOCK; |
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180 |
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181 // Postamble |
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182 for (i = 0; i < 32; i++) { |
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183 MII_SET_CLOCK(0); |
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184 MII_SET_DATA(1); |
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185 CYGACC_CALL_IF_DELAY_US(1); |
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186 MII_SET_CLOCK(1); |
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187 CYGACC_CALL_IF_DELAY_US(1); |
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188 } |
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189 |
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190 return retval; |
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191 } |
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192 |
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193 // |
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194 // PHY unit access (via MII channel) |
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195 // |
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196 static void |
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197 phy_write(int reg, int addr, unsigned short data) |
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198 { |
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199 phy_cmd(MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data); |
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200 } |
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201 |
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202 static bool |
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203 phy_read(int reg, int addr, unsigned short *val) |
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204 { |
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205 cyg_uint32 ret; |
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206 |
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207 ret = phy_cmd(MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA); |
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208 *val = ret; |
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209 return true; |
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210 } |
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211 |
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212 bool |
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213 _adder_reset_phy(void) |
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214 { |
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215 volatile EPPC *eppc = (volatile EPPC *)eppc_base(); |
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216 int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear |
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217 bool phy_ok; |
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218 unsigned short phy_state = 0; |
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219 int phy_unit = -1; |
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220 int i; |
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221 |
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222 // Reset PHY (transceiver) |
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223 eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip |
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224 CYGACC_CALL_IF_DELAY_US(15000); // > 10ms |
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225 eppc->pip_pbdat |= 0x00004000; // Enable PHY chip |
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226 |
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227 phy_ok = false; |
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228 |
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229 // Try and discover how this PHY is wired |
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230 for (i = 0; i < 0x20; i++) { |
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231 phy_read(PHY_BMCR, i, &phy_state); |
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232 if ((phy_state & PHY_BMCR_RESET) == 0) { |
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233 phy_unit = i; |
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234 break; |
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235 } |
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236 } |
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237 if (phy_unit < 0) { |
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238 diag_printf("QUICC ETH - Can't locate PHY\n"); |
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239 return false; |
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240 } else { |
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241 #if 0 |
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242 diag_printf("QUICC ETH - using PHY %d\n", phy_unit); |
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243 #endif |
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244 } |
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245 if (phy_read(PHY_BMSR, phy_unit, &phy_state)) { |
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246 if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) { |
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247 unsigned short reset_mode; |
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248 phy_write(PHY_BMCR, phy_unit, PHY_BMCR_RESET); |
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249 for (i = 0; i < 10; i++) { |
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250 phy_ok = phy_read(PHY_BMCR, phy_unit, &phy_state); |
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251 if (!phy_ok) break; |
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252 if (!(phy_state & PHY_BMCR_RESET)) break; |
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253 } |
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254 if (!phy_ok || (phy_state & PHY_BMCR_RESET)) { |
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255 diag_printf("QUICC/ETH: Can't get PHY unit to soft reset: %x\n", phy_state); |
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256 return false; |
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257 } |
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258 reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX; |
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259 phy_write(PHY_BMCR, phy_unit, reset_mode); |
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260 while (phy_timeout-- >= 0) { |
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261 phy_ok = phy_read(PHY_BMSR, phy_unit, &phy_state); |
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262 if (phy_ok && (phy_state & PHY_BMSR_LINK)) { |
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263 break; |
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264 } else { |
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265 CYGACC_CALL_IF_DELAY_US(10000); // 10ms |
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266 } |
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267 } |
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268 if (phy_timeout <= 0) { |
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269 diag_printf("** QUICC/ETH Warning: PHY LINK UP failed\n"); |
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270 } |
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271 } |
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272 else { |
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273 diag_printf("** QUICC/ETH Info: PHY LINK already UP \n"); |
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274 } |
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275 } |
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276 |
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277 return phy_ok; |
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278 } |
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279 |
