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annotate packages/hal/arm/arm9/var/current/include/hal_cache.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children 7799e045560b
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): gthomas
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47 // Contributors:hmt, jskov
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48 // Travis C. Furrer <furrer@mit.edu>
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49 // Date: 2000-05-08
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50 // Purpose: Cache control API
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51 // Description: The macros defined here provide the HAL APIs for handling
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52 // cache control operations.
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53 // Usage:
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54 // #include <cyg/hal/hal_cache.h>
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55 // ...
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56 //
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57 //
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58 //####DESCRIPTIONEND####
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59 //
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60 //=============================================================================
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61
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62 #include <cyg/infra/cyg_type.h>
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63 #include <cyg/hal/hal_mmu.h>
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64
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66 //-----------------------------------------------------------------------------
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67 // Cache dimensions
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68
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69 #if defined(CYGPKG_HAL_ARM_ARM9_ARM920T)
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70 # define HAL_ICACHE_SIZE 0x4000
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71 # define HAL_ICACHE_LINE_SIZE 32
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72 # define HAL_ICACHE_WAYS 64
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73 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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74
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75 # define HAL_DCACHE_SIZE 0x4000
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76 # define HAL_DCACHE_LINE_SIZE 32
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77 # define HAL_DCACHE_WAYS 64
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78 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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79
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80 # define HAL_WRITE_BUFFER 64
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81
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82 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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83 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
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84 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
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85
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86 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
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87 # define HAL_ICACHE_SIZE 0x2000
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88 # define HAL_ICACHE_LINE_SIZE 32
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89 # define HAL_ICACHE_WAYS 64
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90 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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91
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92 # define HAL_DCACHE_SIZE 0x2000
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93 # define HAL_DCACHE_LINE_SIZE 32
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94 # define HAL_DCACHE_WAYS 64
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95 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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96
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97 # define HAL_WRITE_BUFFER 64
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98
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99 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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100 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
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101 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
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102
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103 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM925T)
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104 # define HAL_ICACHE_SIZE 0x4000
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105 # define HAL_ICACHE_LINE_SIZE 32
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106 # define HAL_ICACHE_WAYS 2
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107 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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108
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109 # define HAL_DCACHE_SIZE 0x2000
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110 # define HAL_DCACHE_LINE_SIZE 32
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111 # define HAL_DCACHE_WAYS 2
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112 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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113
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114 # define HAL_WRITE_BUFFER 64
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115
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116 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE // has instruction to clean D-cache
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117
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118 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
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119 # define HAL_ICACHE_SIZE 0x1000
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120 # define HAL_ICACHE_LINE_SIZE 16
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121 # define HAL_ICACHE_WAYS 4
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122 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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123
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124 # define HAL_DCACHE_SIZE 0x1000
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125 # define HAL_DCACHE_LINE_SIZE 16
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126 # define HAL_DCACHE_WAYS 4
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127 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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128
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129 # define HAL_WRITE_BUFFER 32
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131 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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132 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x10
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133 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
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135 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM966E)
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136 # define HAL_ICACHE_SIZE 0
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137 # define HAL_ICACHE_LINE_SIZE 0
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138 # define HAL_ICACHE_WAYS 0
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139 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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140
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141 # define HAL_DCACHE_SIZE 0
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142 # define HAL_DCACHE_LINE_SIZE 0
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143 # define HAL_DCACHE_WAYS 0
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144 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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145
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146 # define HAL_WRITE_BUFFER 32
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147
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148 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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149 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0
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150 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0
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151
178
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152 #else
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153 # error "No cache details defined"
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154 #endif
169
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155
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156 // FIXME: much of the code below should make better use of
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157 // the definitions from hal_mmu.h
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158
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159 //-----------------------------------------------------------------------------
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160 // Global control of Instruction cache
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161
208
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162 #if HAL_ICACHE_SIZE != 0
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163
169
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164 // FIXME: disable/enable instruction streaming?
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165
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166 // Enable the instruction cache
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167 #define HAL_ICACHE_ENABLE() \
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168 CYG_MACRO_START \
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169 asm volatile ( \
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170 "mrc p15,0,r1,c1,c0,0;" \
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171 "orr r1,r1,#0x1000;" \
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172 "orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
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173 /* that MMU and alignment faults */ \
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174 /* are enabled) */ \
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175 "mcr p15,0,r1,c1,c0,0" \
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176 : \
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177 : \
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178 : "r1" /* Clobber list */ \
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179 ); \
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180 CYG_MACRO_END
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181
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182 // Disable the instruction cache (and invalidate it, required semanitcs)
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183 #define HAL_ICACHE_DISABLE() \
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184 CYG_MACRO_START \
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185 asm volatile ( \
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186 "mrc p15,0,r1,c1,c0,0;" \
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187 "bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
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188 "mcr p15,0,r1,c1,c0,0;" \
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189 "mov r1,#0;" \
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190 "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
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191 "nop;" /* next few instructions may be via cache */ \
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192 "nop;" \
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193 "nop;" \
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194 "nop;" \
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195 "nop;" \
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196 "nop" \
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197 : \
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198 : \
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199 : "r1" /* Clobber list */ \
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200 ); \
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201 CYG_MACRO_END
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202
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203 // Query the state of the instruction cache
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204 #define HAL_ICACHE_IS_ENABLED(_state_) \
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205 CYG_MACRO_START \
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206 register cyg_uint32 reg; \
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207 asm volatile ("mrc p15,0,%0,c1,c0,0" \
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208 : "=r"(reg) \
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209 : \
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210 ); \
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211 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
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212 CYG_MACRO_END
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213
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214 // Invalidate the entire cache
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215 #define HAL_ICACHE_INVALIDATE_ALL() \
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216 CYG_MACRO_START \
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217 /* this macro can discard dirty cache lines (N/A for ICache) */ \
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218 asm volatile ( \
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219 "mov r1,#0;" \
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220 "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
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221 "mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
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222 "nop;" /* next few instructions may be via cache */ \
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223 "nop;" \
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224 "nop;" \
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225 "nop;" \
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226 "nop;" \
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227 "nop;" \
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228 : \
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229 : \
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230 : "r1" /* Clobber list */ \
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231 ); \
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232 CYG_MACRO_END
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233
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234 // Synchronize the contents of the cache with memory.
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235 // (which includes flushing out pending writes)
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236 #define HAL_ICACHE_SYNC() \
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237 CYG_MACRO_START \
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238 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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239 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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240 CYG_MACRO_END
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241
208
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242 #else
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243
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244 #define HAL_ICACHE_ENABLE()
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245 #define HAL_ICACHE_DISABLE()
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246 #define HAL_ICACHE_IS_ENABLED(_state_) ((_state_) = 0)
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247 #define HAL_ICACHE_INVALIDATE_ALL()
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248 #define HAL_ICACHE_SYNC()
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249
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250 #endif
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251
169
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252 // Set the instruction cache refill burst size
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253 //#define HAL_ICACHE_BURST_SIZE(_size_)
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254
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255 // Load the contents of the given address range into the instruction cache
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256 // and then lock the cache so that it stays there.
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257 //#define HAL_ICACHE_LOCK(_base_, _size_)
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258
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259 // Undo a previous lock operation
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260 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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261
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262 // Unlock entire cache
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263 //#define HAL_ICACHE_UNLOCK_ALL()
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264
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265 //-----------------------------------------------------------------------------
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266 // Instruction cache line control
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267
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268 // Invalidate cache lines in the given range without writing to memory.
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269 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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270
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271 //-----------------------------------------------------------------------------
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272 // Global control of data cache
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273
208
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274 #if HAL_DCACHE_SIZE != 0
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275
169
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276 // Enable the data cache
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277 #define HAL_DCACHE_ENABLE() \
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278 CYG_MACRO_START \
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279 asm volatile ( \
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280 "mrc p15,0,r1,c1,c0,0;" \
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281 "orr r1,r1,#0x000F;" /* enable DCache (also ensures */ \
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282 /* the MMU, alignment faults, and */ \
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283 /* write buffer are enabled) */ \
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284 "mcr p15,0,r1,c1,c0,0" \
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285 : \
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286 : \
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287 : "r1" /* Clobber list */ \
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288 ); \
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289 CYG_MACRO_END
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290
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291 // Disable the data cache (and invalidate it, required semanitcs)
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292 #define HAL_DCACHE_DISABLE() \
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293 CYG_MACRO_START \
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294 asm volatile ( \
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295 "mrc p15,0,r1,c1,c0,0;" \
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296 "bic r1,r1,#0x000C;" /* disable DCache AND write buffer */ \
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297 /* but not MMU and alignment faults */ \
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298 "mcr p15,0,r1,c1,c0,0;" \
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299 "mov r1,#0;" \
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300 "mcr p15,0,r1,c7,c6,0" /* clear data cache */ \
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301 : \
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302 : \
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303 : "r1" /* Clobber list */ \
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304 ); \
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305 CYG_MACRO_END
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306
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307 // Query the state of the data cache
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308 #define HAL_DCACHE_IS_ENABLED(_state_) \
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309 CYG_MACRO_START \
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310 register int reg; \
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311 asm volatile ("mrc p15,0,%0,c1,c0,0;" \
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312 : "=r"(reg) \
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313 : \
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314 ); \
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315 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
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316 CYG_MACRO_END
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317
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318 // Flush the entire dcache (and then both TLBs, just in case)
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319 #define HAL_DCACHE_INVALIDATE_ALL() \
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320 CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
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321 asm volatile ( \
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322 "mov r0,#0;" \
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323 "mcr p15,0,r0,c7,c6,0;" /* flush d-cache */ \
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324 "mcr p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */ \
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325 : \
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326 : \
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327 : "r0","memory" /* clobber list */); \
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328 CYG_MACRO_END
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329
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330 // Synchronize the contents of the cache with memory.
178
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331 #ifdef CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE
169
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332 #define HAL_DCACHE_SYNC() \
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333 CYG_MACRO_START \
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334 asm volatile ( \
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335 "mov r0, #0;" \
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336 "mcr p15,0,r0,c7,c10,0;" /* clean DCache */ \
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337 "1: mrc p15,0,r0,c15,c4,0;" /* wait for dirty flag to clear */ \
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338 "ands r0,r0,#0x80000000;" \
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339 "bne 1b;" \
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340 "mov r0,#0;" \
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341 "mcr p15,0,r0,c7,c6,0;" /* flush DCache */ \
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342 "mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
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343 : \
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344 : \
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345 : "r0" /* Clobber list */ \
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346 ); \
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347 CYG_MACRO_END
178
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348 #elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
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349 #define HAL_DCACHE_SYNC() \
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350 CYG_MACRO_START \
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351 cyg_uint32 _tmp1, _tmp2; \
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352 asm volatile ( \
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353 "mov %0, #0;" \
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354 "1: " \
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355 "mov %1, #0;" \
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356 "2: " \
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357 "orr r0,%0,%1;" \
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358 "mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
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359 "add %1,%1,%2;" \
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360 "cmp %1,%3;" \
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361 "bne 2b;" \
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362 "add %0,%0,#0x04000000;" /* get to next index */ \
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363 "cmp %0,#0;" \
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364 "bne 1b;" \
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365 "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
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366 : "=r" (_tmp1), "=r" (_tmp2) \
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367 : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
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368 "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
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369 : "r0" /* Clobber list */ \
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370 ); \
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371 CYG_MACRO_END
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372 #else
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373 # error "Don't know how to sync Dcache"
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374 #endif
169
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375
208
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376 #else
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377
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378 #define HAL_DCACHE_ENABLE()
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379 #define HAL_DCACHE_DISABLE()
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380 #define HAL_DCACHE_IS_ENABLED(_state_) ((_state_) = 0)
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381 #define HAL_DCACHE_INVALIDATE_ALL()
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382 #define HAL_DCACHE_SYNC()
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383
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384 #endif
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385
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386
169
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387 // Set the data cache refill burst size
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388 //#define HAL_DCACHE_BURST_SIZE(_size_)
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389
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390 // Set the data cache write mode
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391 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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392
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393 #define HAL_DCACHE_WRITETHRU_MODE 0
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394 #define HAL_DCACHE_WRITEBACK_MODE 1
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395
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396 // Get the current writeback mode - or only writeback mode if fixed
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397 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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398 _mode_ = HAL_DCACHE_WRITEBACK_MODE; \
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399 CYG_MACRO_END
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400
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401 // Load the contents of the given address range into the data cache
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402 // and then lock the cache so that it stays there.
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403 //#define HAL_DCACHE_LOCK(_base_, _size_)
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404
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405 // Undo a previous lock operation
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406 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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407
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408 // Unlock entire cache
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409 //#define HAL_DCACHE_UNLOCK_ALL()
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410
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411 //-----------------------------------------------------------------------------
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412 // Data cache line control
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413
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414 // Allocate cache lines for the given address range without reading its
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415 // contents from memory.
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416 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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417
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418 // Write dirty cache lines to memory and invalidate the cache entries
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419 // for the given address range.
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420 // ---- this seems not to work despite the documentation ---
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421 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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422 //CYG_MACRO_START
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423 // HAL_DCACHE_STORE( _base_ , _size_ );
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424 // HAL_DCACHE_INVALIDATE( _base_ , _size_ );
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425 //CYG_MACRO_END
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426
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427 // Invalidate cache lines in the given range without writing to memory.
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428 // ---- this seems not to work despite the documentation ---
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429 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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430 //CYG_MACRO_START
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431 // register int addr, enda;
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432 // for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
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433 // enda = (int)(_base_) + (_size_);
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434 // addr < enda ;
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435 // addr += HAL_DCACHE_LINE_SIZE )
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436 // {
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437 // asm volatile (
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438 // "mcr p15,0,%0,c7,c6,1;" /* flush entry away */
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439 // :
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440 // : "r"(addr)
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441 // : "memory"
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442 // );
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443 // }
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444 //CYG_MACRO_END
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445
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446 // Write dirty cache lines to memory for the given address range.
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447 // ---- this seems not to work despite the documentation ---
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448 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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449 //CYG_MACRO_START
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450 // register int addr, enda;
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451 // for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
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452 // enda = (int)(_base_) + (_size_);
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453 // addr < enda ;
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454 // addr += HAL_DCACHE_LINE_SIZE )
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455 // {
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456 // asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */
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457 // :
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458 // : "r"(addr)
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459 // : "memory"
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460 // );
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461 // }
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462 //CYG_MACRO_END
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463
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464 // Preread the given range into the cache with the intention of reading
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465 // from it later.
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466 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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467
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468 // Preread the given range into the cache with the intention of writing
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469 // to it later.
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470 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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471
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472 // Allocate and zero the cache lines associated with the given range.
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473 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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474
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475 //-----------------------------------------------------------------------------
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476 // Cache controls for safely disabling/reenabling caches around execution
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477 // of relocated code.
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478
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479 #define HAL_FLASH_CACHES_OFF(_d_, _i_) \
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480 CYG_MACRO_START \
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481 HAL_ICACHE_IS_ENABLED(_i_); \
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482 HAL_DCACHE_IS_ENABLED(_d_); \
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483 HAL_ICACHE_INVALIDATE_ALL(); \
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484 HAL_ICACHE_DISABLE(); \
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485 HAL_DCACHE_SYNC(); \
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486 HAL_DCACHE_INVALIDATE_ALL(); \
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487 HAL_DCACHE_DISABLE(); \
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488 CYG_MACRO_END
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489
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490 #define HAL_FLASH_CACHES_ON(_d_, _i_) \
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491 CYG_MACRO_START \
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492 if (_d_) HAL_DCACHE_ENABLE(); \
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493 if (_i_) HAL_ICACHE_ENABLE(); \
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494 CYG_MACRO_END
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495
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496 //-----------------------------------------------------------------------------
196
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497 // Virtual<->Physical translations
208
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498 #ifndef HAL_VIRT_TO_PHYS_ADDRESS
196
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499 extern cyg_uint32 hal_virt_to_phys_address(cyg_uint32 phys);
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500 #define HAL_VIRT_TO_PHYS_ADDRESS(_va, _pa) \
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501 _pa = hal_virt_to_phys_address(_va)
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502 #endif
196
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503 //-----------------------------------------------------------------------------
169
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504 #endif // ifndef CYGONCE_HAL_CACHE_H
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505 // End of hal_cache.h