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annotate packages/hal/arm/integrator/current/src/integrator_misc.c @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 //==========================================================================
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2 //
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3 // integrator_misc.c
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4 //
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5 // HAL misc board support code for ARM INTEGRATOR7
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): David A Rusling
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44 // Contributors: Philippe Robin
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45 // Date: November 7, 2000
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46 // Purpose: HAL board support
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47 // Description: Implementations of HAL board interfaces
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //===========================================================================*/
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52
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53 #include <pkgconf/hal.h>
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54
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55 #include <cyg/infra/cyg_type.h> // base types
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56 #include <cyg/infra/cyg_trac.h> // tracing macros
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57 #include <cyg/infra/cyg_ass.h> // assertion macros
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58
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59 #include <cyg/hal/hal_io.h> // IO macros
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60 #include <cyg/hal/hal_arch.h> // Register state info
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61 #include <cyg/hal/hal_diag.h>
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62 #include <cyg/hal/hal_intr.h> // necessary?
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63 #include <cyg/hal/hal_integrator.h>
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64
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65 /*------------------------------------------------------------------------*/
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66 // On-board timer
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67 /*------------------------------------------------------------------------*/
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68
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69 // forward declarations
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70 void hal_if_init(void);
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71
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72 // declarations
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73 static cyg_uint32 _period;
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74
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75 void hal_clock_initialize(cyg_uint32 period)
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76 {
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77 //diag_init(); diag_printf("%s(%d)\n", __PRETTY_FUNCTION__, period);
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78 //diag_printf("psr = %x\n", psr());
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79 HAL_WRITE_UINT32(CYG_DEVICE_TIMER_CONTROL, CTL_DISABLE); // Turn off
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80 HAL_WRITE_UINT32(CYG_DEVICE_TIMER_LOAD, period);
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81 HAL_WRITE_UINT32(CYG_DEVICE_TIMER_CONTROL,
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82 CTL_ENABLE | CTL_PERIODIC | CTL_SCALE_16);
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83 _period = period;
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84 }
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85
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86 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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87 {
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88 //diag_init(); diag_printf("%s\n", __PRETTY_FUNCTION__);
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89 HAL_WRITE_UINT32(CYG_DEVICE_TIMER_CLEAR, 0);
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90 _period = period;
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91 }
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92
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93 void hal_clock_read(cyg_uint32 *pvalue)
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94 {
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95 cyg_uint32 value;
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96 // diag_init(); diag_printf("%s\n", __PRETTY_FUNCTION__);
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97 HAL_READ_UINT32(CYG_DEVICE_TIMER_CURRENT, value);
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98 value &= 0xFFFF;
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99 *pvalue = _period - (value & 0xFFFF); // Note: counter is only 16 bits
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100 // and decreases
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101 }
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102
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103 // Delay for some usecs.
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104 void hal_delay_us(cyg_uint32 delay)
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105 {
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106 #if 0
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107 int i;
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108 for( i = 0; i < delay; i++ );
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109
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110 #else
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111 cyg_uint32 now, last, diff, ticks;
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112
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113 // The timer actually runs at 1.25 ticks per micrsecond.
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114 // Adjust the supplied delay to compensate.
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115
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116 delay *= 4;
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117 delay /= 5;
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118
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119 hal_clock_read(&last);
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120 diff = ticks = 0;
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121
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122 while (delay > ticks) {
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123 hal_clock_read(&now);
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124
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125 // Cope with wrap-around of timer
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126 if (now < last)
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127 diff = ((_period - last) + now);
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128 else
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129 diff = (now - last);
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130
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131 last = now;
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132
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133 ticks += diff;
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134 }
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135 #endif
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136 }
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137
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138
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139 #if defined(CYGPKG_HAL_ARM_INTEGRATOR_ARM7)
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140 void hal_hardware_init(void)
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141 #elif defined(CYGPKG_HAL_ARM_INTEGRATOR_ARM9)
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142 void plf_hardware_init(void)
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143 #endif
195
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144 {
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145 // Any hardware/platform initialization that needs to be done.
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146
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147 // Clear all interrupt sources
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148 HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 0xFFFF);
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149
208
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150 #ifndef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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151 HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
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152 #endif
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153
195
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154 // FIXME: The line with the thumb check is a hack, allowing
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155 // the farm to run test. Problem is that virtual vector table
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156 // API needs to be ARM/Thumb consistent. Will fix later.
208
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157 #if !defined(__thumb__) && !defined(CYGPKG_HAL_ARM_INTEGRATOR_ARM9)
195
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158 // Set up eCos/ROM interfaces
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159 hal_if_init();
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160 #endif
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161 }
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162
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163 //
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164 // This routine is called to respond to a hardware interrupt (IRQ). It
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165 // should interrogate the hardware and return the IRQ vector number.
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166
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167 int hal_IRQ_handler(void)
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168 {
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169 // Do hardware-level IRQ handling
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170 int irq_status, vector;
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171 HAL_READ_UINT32(CYG_DEVICE_IRQ_Status, irq_status);
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172 //diag_init(); diag_printf("IRQ status: 0x%x\n", irq_status);
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173 for (vector = 1; vector <= 16; vector++) {
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174 if (irq_status & (1<<vector)) return vector;
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175 }
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176 return -1 ; // This shouldn't happen!
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177 }
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178
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179 //
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180 // Interrupt control
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181 //
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182
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183 void hal_interrupt_mask(int vector)
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184 {
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185 //diag_init(); diag_printf("hal_interrupt_mask(%d)\n", vector);
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186 HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 1<<vector);
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187 }
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188
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189 #if 0
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190 void hal_interrupt_status(void)
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191 {
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192 int irq_status, irq_enable, timer_status, timer_value, timer_load;
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193 HAL_READ_UINT32(CYG_DEVICE_IRQ_Status, irq_status);
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194 HAL_READ_UINT32(CYG_DEVICE_IRQ_Enable, irq_enable);
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195 HAL_READ_UINT32(CYG_DEVICE_TIMER_LOAD, timer_load);
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196 HAL_READ_UINT32(CYG_DEVICE_TIMER_CURRENT, timer_value);
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197 HAL_READ_UINT32(CYG_DEVICE_TIMER_CONTROL, timer_status);
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198 diag_printf("Interrupt: IRQ: %x.%x, TIMER: %x.%x.%x, psr: %x\n",
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199 irq_status, irq_enable, timer_status, timer_value,
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200 timer_load, psr());
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201 }
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202 #endif
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203
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204 void hal_interrupt_unmask(int vector)
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205 {
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206 //diag_init(); diag_printf("hal_interrupt_unmask(%d)\n", vector);
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207 HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableSet, 1<<vector);
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208 }
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209
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210 void hal_interrupt_acknowledge(int vector)
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211 {
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212 //diag_init(); diag_printf("%s(%d)\n", __PRETTY_FUNCTION__, vector);
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213 }
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214
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215 void hal_interrupt_configure(int vector, int level, int up)
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216 {
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217 //diag_init(); diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up);
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218 }
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219
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220 void hal_interrupt_set_level(int vector, int level)
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221 {
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222 //diag_init(); diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level);
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223 }
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224
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225 void hal_show_IRQ(int vector, int data, int handler)
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226 {
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227 // diag_printf("IRQ - vector: %x, data: %x, handler: %x\n", vector, data, handler);
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228 }
208
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229
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230 /*---------------------------------------------------------------------------*/
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231
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232 __externC void cyg_plf_pci_init(void)
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233 {
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234 // Only do this for non-RAM startups. If we do it during RAM
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235 // startup and we are using the ethernet for debugging, this kills
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236 // the ethernet controller.
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237 #ifndef CYG_HAL_STARTUP_RAM
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238
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239 volatile int i, j;
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240
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241 /* setting this register will take the V3 out of reset */
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242
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243 *(volatile cyg_uint32 *)(INTEGRATOR_SC_PCIENABLE) = 1;
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244
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245 /* wait a few usecs to settle the device and the PCI bus */
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246
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247 for (i = 0; i < 100 ; i++)
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248 j = i + 1;
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249
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250 /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
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251
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252 *(volatile cyg_uint16 *)(V3_BASE + V3_LB_IO_BASE) = (cyg_uint16)(V3_BASE >> 16);
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253
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254 do {
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255 *(volatile cyg_uint8 *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
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256 *(volatile cyg_uint8 *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
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257 } while (*(volatile cyg_uint8 *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
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258 *(volatile cyg_uint8 *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
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259
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260 /* Make sure that V3 register access is not locked, if it is, unlock it */
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261
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262 if ((*(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
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263 == V3_SYSTEM_M_LOCK)
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264 *(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM) = 0xA05F;
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265
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266 /* Ensure that the slave accesses from PCI are disabled while we */
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267 /* setup windows */
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268
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269 *(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CMD) &=
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270 ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
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271
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272 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
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273
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274 *(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
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275
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276 /* Make all accesses from PCI space retry until we're ready for them */
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277
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278 *(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
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279
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280 /* Set up any V3 PCI Configuration Registers that we absolutely have to */
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281 /* LB_CFG controls Local Bus protocol. */
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282 /* Enable LocalBus byte strobes for READ accesses too. */
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283 /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
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284
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285 *(volatile cyg_uint16 *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
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286
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287 /* PCI_CMD controls overall PCI operation. */
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288 /* Enable PCI bus master. */
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289
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290 *(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CMD) |= 0x04;
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291
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292 /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
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293
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294 *(volatile cyg_uint32 *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
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295 (V3_PCI_MAP_M_ADR_SIZE_512M |
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296 V3_PCI_MAP_M_REG_EN |
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297 V3_PCI_MAP_M_ENABLE);
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298
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299 /* PCI_BASE0 is the PCI address of the start of the window */
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300
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301 *(volatile cyg_uint32 *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
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302
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303 /* PCI_MAP1 is LOCAL address of the start of the window */
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304
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305 *(volatile cyg_uint32 *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
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306 (V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
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307 V3_PCI_MAP_M_ENABLE);
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308
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309 /* PCI_BASE1 is the PCI address of the start of the window */
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310
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311 *(volatile cyg_uint32 *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
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312
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313 /* Set up the windows from local bus memory into PCI configuration, */
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314 /* I/O and Memory. */
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315 /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
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316
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317 *(volatile cyg_uint16 *)(V3_BASE +V3_LB_BASE2) =
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318 ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
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319 *(volatile cyg_uint16 *)(V3_BASE + V3_LB_MAP2) = 0;
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320
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321 /* PCI Configuration, use LB_BASE1/LB_MAP1. */
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322
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323 /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
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324 /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
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325 /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
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326
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327 *(volatile cyg_uint32 *)(V3_BASE + V3_LB_BASE0) =
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328 INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
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329
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330 *(volatile cyg_uint16 *)(V3_BASE + V3_LB_MAP0) =
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331 ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
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332
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333 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
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334
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335 *(volatile cyg_uint32 *)(V3_BASE + V3_LB_BASE1) =
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336 INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
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337
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338 *(volatile cyg_uint16 *)(V3_BASE + V3_LB_MAP1) =
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339 (((INTEGRATOR_PCI_BASE + SZ_256M) >> 20) << 4) | 0x0006;
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340
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341 /* Allow accesses to PCI Configuration space */
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342 /* and set up A1, A0 for type 1 config cycles */
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343
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344 *(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CFG) =
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345 ((*(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CFG)) &
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346 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
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347 V3_PCI_CFG_M_AD_LOW0;
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348
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349 /* now we can allow in PCI MEMORY accesses */
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350
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351 *(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CMD) =
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352 (*(volatile cyg_uint16 *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
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353
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354 /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
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355 /* initialise and lock the V3 system register so that no one else */
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356 /* can play with it */
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357
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358 *(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM) =
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359 (*(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
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360
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361 *(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM) =
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362 (*(volatile cyg_uint16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
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363
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364 #endif
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365 }
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366
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367 /*---------------------------------------------------------------------------*/
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368 /* End of hal_misc.c */