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annotate packages/hal/mips/tx49/current/include/var_cache.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors:nickg, jskov
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48 // Date: 2000-05-09
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/imp_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <pkgconf/hal.h>
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62 #include <cyg/infra/cyg_type.h>
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63
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64 #include <cyg/hal/mips-regs.h>
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65
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66 #include <cyg/hal/plf_cache.h>
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67
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68 //=============================================================================
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69 // Toshiba TX4955
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70
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71 #ifdef CYGPKG_HAL_MIPS_TX4955
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72
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73 //-----------------------------------------------------------------------------
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74 // Cache dimensions
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75
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76 // Data cache
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77 #define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes
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78 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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79 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
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80
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81 // Instruction cache
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82 #define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes
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83 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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84 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
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85
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86 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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87 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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88
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89 #define HAL_MIPS_CACHE_INSN_USES_LSB
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90
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91 //-----------------------------------------------------------------------------
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92 // Cache controls
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93
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94 // Register $16 is Config register (controls cache state)
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95
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96 // Config Register fields
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97 #define CYGARC_REG_CONFIG_ICE 0x00020000 // Instruction cache enable
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98 #define CYGARC_REG_CONFIG_DCE 0x00010000 // Data cache enable
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99
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100
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101 //-----------------------------------------------------------------------------
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102 // Global control of data cache
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103
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104 // Enable the data cache
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105 // This uses a bit in the config register, which is TX49 specific.
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106 #define HAL_DCACHE_ENABLE_DEFINED
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107 #define HAL_DCACHE_ENABLE() \
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108 CYG_MACRO_START \
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109 cyg_uint32 tmp; \
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110 asm volatile ("mfc0 %0,$16;" \
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111 "and %0,%0,%1;" \
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112 "mtc0 %0,$16;" \
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113 : "=&r" (tmp) \
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114 : "r" (~CYGARC_REG_CONFIG_DCE) \
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115 ); \
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116 CYG_MACRO_END
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117
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118 // Disable the data cache
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119 #define HAL_DCACHE_DISABLE_DEFINED
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120 #define HAL_DCACHE_DISABLE() \
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121 CYG_MACRO_START \
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122 cyg_uint32 tmp; \
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123 asm volatile ("mfc0 %0,$16;" \
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124 "or %0,%0,%1;" \
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125 "mtc0 %0,$16;" \
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126 : "=&r" (tmp) \
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127 : "r" (CYGARC_REG_CONFIG_DCE) \
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128 ); \
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129 CYG_MACRO_END
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130
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131 #define HAL_DCACHE_IS_ENABLED_DEFINED
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132 #define HAL_DCACHE_IS_ENABLED(_state_) \
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133 CYG_MACRO_START \
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134 cyg_uint32 _cstate_; \
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135 asm volatile ( "mfc0 %0,$16\n" \
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136 : "=r"(_cstate_) \
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137 ); \
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138 if( _cstate_ & CYGARC_REG_CONFIG_DCE) \
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139 _state_ = 0; \
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140 else \
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141 _state_ = 1; \
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142 CYG_MACRO_END
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143
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144 // Architecture HAL defines other operations
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145
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146
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147 //-----------------------------------------------------------------------------
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148 // Global control of Instruction cache
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149
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150 // Enable the instruction cache
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151 #define HAL_ICACHE_ENABLE_DEFINED
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152 #define HAL_ICACHE_ENABLE() \
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153 CYG_MACRO_START \
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154 cyg_uint32 tmp; \
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155 asm volatile ("mfc0 %0,$16;" \
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156 "and %0,%0,%1;" \
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157 "mtc0 %0,$16;" \
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158 : "=&r" (tmp) \
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159 : "r" (~CYGARC_REG_CONFIG_ICE) \
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160 ); \
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161 CYG_MACRO_END
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162
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163 // Disable the instruction cache
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164 #define HAL_ICACHE_DISABLE_DEFINED
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165 #define HAL_ICACHE_DISABLE() \
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166 CYG_MACRO_START \
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167 cyg_uint32 tmp; \
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168 asm volatile ("mfc0 %0,$16;" \
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169 "or %0,%0,%1;" \
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170 "mtc0 %0,$16;" \
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171 : "=&r" (tmp) \
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172 : "r" (CYGARC_REG_CONFIG_ICE) \
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173 ); \
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174 CYG_MACRO_END
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175
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176 #define HAL_ICACHE_IS_ENABLED_DEFINED
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177 #define HAL_ICACHE_IS_ENABLED(_state_) \
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178 CYG_MACRO_START \
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179 cyg_uint32 _cstate_; \
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180 asm volatile ( "mfc0 %0,$16\n" \
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181 : "=r"(_cstate_) \
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182 ); \
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183 if( _cstate_ & CYGARC_REG_CONFIG_ICE) \
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184 _state_ = 0; \
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185 else \
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186 _state_ = 1; \
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187 CYG_MACRO_END
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188
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189 // TX49 cache instruction must not affect the line it executes out of,
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190 // so disable instruction cache before invalidating it.
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191 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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192 #define HAL_ICACHE_INVALIDATE_ALL() \
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193 CYG_MACRO_START \
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194 register CYG_ADDRESS _baddr_ = 0x80000000; \
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195 register CYG_ADDRESS _addr_ = 0x80000000; \
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196 register CYG_WORD _state_; \
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197 _HAL_ASM_SET_MIPS_ISA(3); \
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198 HAL_ICACHE_IS_ENABLED( _state_ ); \
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199 HAL_ICACHE_DISABLE(); \
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200 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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201 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
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202 if( _state_ ) HAL_ICACHE_ENABLE(); \
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203 _HAL_ASM_SET_MIPS_ISA(0); \
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204 CYG_MACRO_END
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205
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206 // Architecture HAL defines other operations
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207
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208 #endif // CYGPKG_HAL_MIPS_TX4955
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209
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210
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211 //-----------------------------------------------------------------------------
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212 #endif // ifndef CYGONCE_VAR_CACHE_H
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213 // End of var_cache.h