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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors: nickg, dmoseley
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48 // Date: 1998-02-17
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/var_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <pkgconf/hal.h>
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62 #include <cyg/infra/cyg_type.h>
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63
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64 //#include <cyg/hal/plf_cache.h>
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65
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66 //=============================================================================
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67 // AM33 implementation
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68
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69 //-----------------------------------------------------------------------------
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70 // Cache dimensions
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72
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73 // Data cache
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74 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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75 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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76 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
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77
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78 // Instruction cache
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79 #define HAL_ICACHE_SIZE 8192 // Size of cache in bytes
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80 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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81 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
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82
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83 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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84 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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85
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86 //-----------------------------------------------------------------------------
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87 // Control registers
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88
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89 #define HAL_CHCTR ((volatile CYG_ADDRWORD *)0xC0000070)
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90
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91 #define HAL_CHCTR_ICEN 0x0001
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92 #define HAL_CHCTR_DCEN 0x0002
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93 #define HAL_CHCTR_ICBUSY 0x0004
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94 #define HAL_CHCTR_DCBUSY 0x0008
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95 #define HAL_CHCTR_ICINV 0x0010
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96 #define HAL_CHCTR_DCINV 0x0020
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97 #define HAL_CHCTR_DCWTMD 0x0040
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98 #define HAL_CHCTR_ICWMD 0x0300
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99 #define HAL_CHCTR_DCWMD 0x3000
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100
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101 #define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0xC8400000)
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102 #define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0xC8401000)
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103 #define HAL_DCACHE_PURGE_WAY2 ((volatile CYG_BYTE *)0xC8402000)
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104 #define HAL_DCACHE_PURGE_WAY3 ((volatile CYG_BYTE *)0xC8403000)
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105
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106 //-----------------------------------------------------------------------------
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107 // Global control of data cache
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108
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109 // Enable the data cache
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110 #define HAL_DCACHE_ENABLE() \
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111 { \
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112 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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113 chctr |= HAL_CHCTR_DCEN; \
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114 *HAL_CHCTR = chctr; \
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115 }
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116
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117 // Disable the data cache
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118 #define HAL_DCACHE_DISABLE() \
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119 { \
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120 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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121 chctr &= ~HAL_CHCTR_DCEN; \
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122 *HAL_CHCTR = chctr; \
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123 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
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124 }
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125
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126 // Query the state of the data cache
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127 #define HAL_DCACHE_IS_ENABLED(_state_) \
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128 { \
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129 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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130 _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \
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131 }
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132
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133 // Invalidate the entire cache
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134 #define HAL_DCACHE_INVALIDATE_ALL() \
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135 { \
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136 register CYG_ADDRWORD chctr; \
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137 register CYG_ADDRWORD state; \
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138 HAL_DCACHE_IS_ENABLED(state); \
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139 if (state) \
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140 HAL_DCACHE_DISABLE(); \
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141 chctr = *HAL_CHCTR; \
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142 chctr |= HAL_CHCTR_DCINV; \
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143 *HAL_CHCTR = chctr; \
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144 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
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145 if (state) \
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146 HAL_DCACHE_ENABLE(); \
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147 }
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148
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149 // Synchronize the contents of the cache with memory.
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150 #define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE )
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151
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152 // Set the data cache refill burst size
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153 //#define HAL_DCACHE_BURST_SIZE(_size_)
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154
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155 // Set the data cache write mode
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156 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
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157 { \
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158 register CYG_ADDRWORD chctr; \
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159 register CYG_ADDRWORD state; \
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160 HAL_DCACHE_IS_ENABLED(state); \
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161 if (state) \
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162 HAL_DCACHE_DISABLE(); \
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163 chctr = *HAL_CHCTR; \
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164 chctr &= ~HAL_CHCTR_DCWTMD; \
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165 chctr |= HAL_CHCTR_DCWTMD*(_mode_); \
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166 *HAL_CHCTR = chctr; \
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167 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
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168 if (state) \
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169 HAL_DCACHE_ENABLE(); \
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170 }
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171
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172 #define HAL_DCACHE_WRITEBACK_MODE 0
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173 #define HAL_DCACHE_WRITETHRU_MODE 1
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174
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175 // Load the contents of the given address range into the data cache
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176 // and then lock the cache so that it stays there.
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177 //#define HAL_DCACHE_LOCK(_base_, _size_)
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178
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179 // Undo a previous lock operation
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180 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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181
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182 // Unlock entire cache
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183 //#define HAL_DCACHE_UNLOCK_ALL()
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184
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185 //-----------------------------------------------------------------------------
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186 // Data cache line control
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187
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188 // Allocate cache lines for the given address range without reading its
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189 // contents from memory.
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190 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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191
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192 // Write dirty cache lines to memory and invalidate the cache entries
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193 // for the given address range.
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194 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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195
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196 // Invalidate cache lines in the given range without writing to memory.
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197 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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198
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199 // Write dirty cache lines to memory for the given address range.
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200
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201 // This functionality requires 4 register variables. To prevent register
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202 // spilling, put the code in a separate function.
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203 externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size);
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204
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205 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
115
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206 cyg_hal_dcache_store((CYG_ADDRWORD)(_base_), (_size_))
76
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207
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208 // Preread the given range into the cache with the intention of reading
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209 // from it later.
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210 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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211
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212 // Preread the given range into the cache with the intention of writing
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213 // to it later.
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214 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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215
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216 // Allocate and zero the cache lines associated with the given range.
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217 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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218
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219 //-----------------------------------------------------------------------------
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220 // Global control of Instruction cache
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221
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222 // Enable the instruction cache
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223 #define HAL_ICACHE_ENABLE() \
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224 { \
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225 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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226 chctr |= HAL_CHCTR_ICEN; \
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227 *HAL_CHCTR = chctr; \
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228 }
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229
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230 // Disable the instruction cache
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231 #define HAL_ICACHE_DISABLE() \
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232 { \
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233 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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234 chctr &= ~HAL_CHCTR_ICEN; \
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235 *HAL_CHCTR = chctr; \
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236 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
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237 }
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238
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239 // Query the state of the instruction cache
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240 #define HAL_ICACHE_IS_ENABLED(_state_) \
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241 { \
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242 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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243 _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \
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244 }
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245
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246 // Invalidate the entire cache
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247 #define HAL_ICACHE_INVALIDATE_ALL() \
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248 { \
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249 register CYG_ADDRWORD chctr; \
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250 register CYG_ADDRWORD state; \
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251 HAL_ICACHE_IS_ENABLED(state); \
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252 if (state) \
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253 HAL_ICACHE_DISABLE(); \
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254 chctr = *HAL_CHCTR; \
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255 chctr |= HAL_CHCTR_ICINV; \
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256 *HAL_CHCTR = chctr; \
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257 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
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258 if (state) \
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259 HAL_ICACHE_ENABLE(); \
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260 }
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261
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262 // Synchronize the contents of the cache with memory.
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263 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
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264
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265 // Set the instruction cache refill burst size
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266 //#define HAL_ICACHE_BURST_SIZE(_size_)
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267
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268 // Load the contents of the given address range into the instruction cache
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269 // and then lock the cache so that it stays there.
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270 //#define HAL_ICACHE_LOCK(_base_, _size_)
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271
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272 // Undo a previous lock operation
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273 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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274
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275 // Unlock entire cache
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276 //#define HAL_ICACHE_UNLOCK_ALL()
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277
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278 //-----------------------------------------------------------------------------
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279 // Instruction cache line control
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280
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281 // Invalidate cache lines in the given range without writing to memory.
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282 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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283
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284 //-----------------------------------------------------------------------------
174
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285 // flash caching control
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286 #ifdef CYGSEM_HAL_UNCACHED_FLASH_ACCESS
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287 #define HAL_FLASH_CACHES_OFF(_d_, _i_) \
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288 CYG_MACRO_START \
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289 _d_ = 0; /* avoids warning */ \
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290 _i_ = 0; /* avoids warning */ \
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291 CYG_MACRO_END
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292
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293 #define HAL_FLASH_CACHES_ON(_d_, _i_) \
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294 CYG_MACRO_START \
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295 CYG_MACRO_END
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296 #endif
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297
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298 //-----------------------------------------------------------------------------
76
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299 #endif // ifndef CYGONCE_VAR_CACHE_H
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300 // End of var_cache.h