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annotate packages/hal/powerpc/arch/current/include/hal_arch.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children c9e9d4163174
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1 #ifndef CYGONCE_HAL_ARCH_H
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2 #define CYGONCE_HAL_ARCH_H
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3
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4 //=============================================================================
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5 //
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6 // hal_arch.h
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7 //
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8 // Architecture specific abstractions
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors: nickg
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48 // Date: 1997-09-08
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49 // Purpose: Define architecture abstractions
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50 // Usage: #include <cyg/hal/hal_arch.h>
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51
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52 //
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53 //####DESCRIPTIONEND####
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54 //
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55 //=============================================================================
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56
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57 #include <pkgconf/hal.h>
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58 #include <cyg/infra/cyg_type.h>
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59
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60 #include <cyg/hal/ppc_regs.h> // CYGARC_REG_MSR_EE
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61
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62 //-----------------------------------------------------------------------------
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63 // Processor saved states:
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64
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65 typedef struct
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66 {
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67 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS
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68 cyg_uint32 wall_head;
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69 #endif
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70
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71 // These are common to all saved states
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72 cyg_uint32 d[32]; // Data regs
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73 #ifdef CYGHWR_HAL_POWERPC_FPU
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74 double f[32]; // Floating point registers
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75 #endif
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76 cyg_uint32 cr; // Condition Reg
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77 cyg_uint32 xer; // XER
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78 cyg_uint32 lr; // Link Reg
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79 cyg_uint32 ctr; // Count Reg
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80
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81 // These are saved for exceptions and interrupts, but may also
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82 // be saved in a context switch if thread-aware debugging is enabled.
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83 cyg_uint32 msr; // Machine State Reg
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84 cyg_uint32 pc; // Program Counter
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85
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86 // This marks the limit of state saved during a context switch and
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87 // is used to calculate necessary stack allocation for context switches.
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88 // It would probably be better to have a union instead...
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89 cyg_uint32 context_size[0];
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90
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91 // These are only saved for exceptions and interrupts
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92 cyg_uint32 vector; // Vector number
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93
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94 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS
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95 cyg_uint32 wall_tail;
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96 #endif
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97 } HAL_SavedRegisters;
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98
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99 //-----------------------------------------------------------------------------
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100 // Exception handling function.
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101 // This function is defined by the kernel according to this prototype. It is
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102 // invoked from the HAL to deal with any CPU exceptions that the HAL does
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103 // not want to deal with itself. It usually invokes the kernel's exception
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104 // delivery mechanism.
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105
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106 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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107
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108 //-----------------------------------------------------------------------------
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109 // Bit manipulation macros
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110
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111 #define HAL_LSBIT_INDEX(index, mask) \
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112 asm ( "neg 11,%1;" \
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113 "and 11,11,%1;" \
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114 "cntlzw %0,11;" \
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115 "subfic %0,%0,31;" \
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116 : "=r" (index) \
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117 : "r" (mask) \
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118 : "r11" \
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119 );
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120
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121 #define HAL_MSBIT_INDEX(index, mask) \
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122 asm ( "cntlzw %0,%1\n" \
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123 "subfic %0,%0,31;" \
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124 : "=r" (index) \
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125 : "r" (mask) \
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126 );
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127
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128 //-----------------------------------------------------------------------------
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129 // eABI
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130 #define CYGARC_PPC_STACK_FRAME_SIZE 56 // size of a stack frame
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131
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132 //-----------------------------------------------------------------------------
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133 // Context Initialization
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134 // Initialize the context of a thread.
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135 // Arguments:
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136 // _sparg_ name of variable containing current sp, will be written with new sp
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137 // _thread_ thread object address, passed as argument to entry point
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138 // _entry_ entry point address.
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139 // _id_ bit pattern used in initializing registers, for debugging.
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140
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141 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
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142 CYG_MACRO_START \
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143 register CYG_WORD _sp_ = (((CYG_WORD)_sparg_) &~15) \
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144 - CYGARC_PPC_STACK_FRAME_SIZE; \
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145 register HAL_SavedRegisters *_regs_; \
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146 int _i_; \
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147 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
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148 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \
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149 (_regs_)->d[01] = (CYG_WORD)(_sp_); /* SP = top of stack */ \
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150 (_regs_)->d[03] = (CYG_WORD)(_thread_); /* R3 = arg1 = thread ptr */ \
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151 (_regs_)->cr = 0; /* CR = 0 */ \
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152 (_regs_)->xer = 0; /* XER = 0 */ \
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153 (_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \
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154 (_regs_)->pc = (CYG_WORD)(_entry_); /* set PC for thread dbg */ \
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155 (_regs_)->ctr = 0; /* CTR = 0 */ \
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156 (_regs_)->msr = CYGARC_REG_MSR_EE; /* MSR = enable irqs */ \
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157 _sparg_ = (CYG_ADDRESS)_regs_; \
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158 CYG_MACRO_END
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159
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160 //-----------------------------------------------------------------------------
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161 // Context switch macros.
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162 // The arguments are pointers to locations where the stack pointer
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163 // of the current thread is to be stored, and from where the sp of the
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164 // next thread is to be fetched.
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165
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166 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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167 externC void hal_thread_load_context( CYG_ADDRESS to )
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168 __attribute__ ((noreturn));
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169
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170 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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171 hal_thread_switch_context((CYG_ADDRESS)_tspptr_,(CYG_ADDRESS)_fspptr_);
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172
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173 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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174 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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175
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176 //-----------------------------------------------------------------------------
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177 // Execution reorder barrier.
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178 // When optimizing the compiler can reorder code. In multithreaded systems
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179 // where the order of actions is vital, this can sometimes cause problems.
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180 // This macro may be inserted into places where reordering should not happen.
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181
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182 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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183
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184 //-----------------------------------------------------------------------------
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185 // Breakpoint support
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186 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
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187 // if executed.
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188 // HAL_BREAKINST is the value of the breakpoint instruction and
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189 // HAL_BREAKINST_SIZE is its size in bytes.
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190
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191 #define HAL_BREAKPOINT(_label_) \
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192 asm volatile (" .globl " #_label_ ";" \
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193 #_label_":" \
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194 " trap" \
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195 );
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196
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197 #define HAL_BREAKINST 0x7d821008
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198
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199 #define HAL_BREAKINST_SIZE 4
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200
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201 //-----------------------------------------------------------------------------
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202 // Thread register state manipulation for GDB support.
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203
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204 // Translate a stack pointer as saved by the thread context macros above into
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205 // a pointer to a HAL_SavedRegisters structure.
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206 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
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207 (_regs_) = (HAL_SavedRegisters *)(_sp_)
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208
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209 // Copy a set of registers from a HAL_SavedRegisters structure into a
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210 // GDB ordered array.
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211 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
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212 CYG_MACRO_START \
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213 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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214 int _i_; \
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215 \
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216 for( _i_ = 0; _i_ < 32; _i_++ ) \
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217 _regval_[_i_] = (_regs_)->d[_i_]; \
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218 \
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219 _regval_[64] = (_regs_)->pc; \
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220 _regval_[65] = (_regs_)->msr; \
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221 _regval_[66] = (_regs_)->cr; \
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222 _regval_[67] = (_regs_)->lr; \
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223 _regval_[68] = (_regs_)->ctr; \
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224 _regval_[69] = (_regs_)->xer; \
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225 CYG_MACRO_END
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226
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227 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
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228 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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229 CYG_MACRO_START \
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230 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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231 int _i_; \
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232 \
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233 for( _i_ = 0; _i_ < 32; _i_++ ) \
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234 (_regs_)->d[_i_] = _regval_[_i_]; \
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235 \
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236 (_regs_)->pc = _regval_[64]; \
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237 (_regs_)->msr = _regval_[65]; \
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238 (_regs_)->cr = _regval_[66]; \
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239 (_regs_)->lr = _regval_[67]; \
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240 (_regs_)->ctr = _regval_[68]; \
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241 (_regs_)->xer = _regval_[69]; \
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242 CYG_MACRO_END
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243
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244 //-----------------------------------------------------------------------------
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245 // HAL setjmp
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246
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247 typedef struct {
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248 cyg_uint32 sp;
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249 cyg_uint32 r2;
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250 cyg_uint32 r13;
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251 cyg_uint32 r14;
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252 cyg_uint32 r15;
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253 cyg_uint32 r16;
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254 cyg_uint32 r17;
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255 cyg_uint32 r18;
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256 cyg_uint32 r19;
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257 cyg_uint32 r20;
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258 cyg_uint32 r21;
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259 cyg_uint32 r22;
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260 cyg_uint32 r23;
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261 cyg_uint32 r24;
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262 cyg_uint32 r25;
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263 cyg_uint32 r26;
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264 cyg_uint32 r27;
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265 cyg_uint32 r28;
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266 cyg_uint32 r29;
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267 cyg_uint32 r30;
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268 cyg_uint32 r31;
208
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269 #ifdef CYGHWR_HAL_POWERPC_FPU
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270 double f14;
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271 double f15;
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272 double f16;
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273 double f17;
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274 double f18;
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275 double f19;
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276 double f20;
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277 double f21;
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278 double f22;
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279 double f23;
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280 double f24;
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281 double f25;
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282 double f26;
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283 double f27;
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284 double f28;
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285 double f29;
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286 double f30;
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287 double f31;
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288 #endif
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289 cyg_uint32 lr;
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290 cyg_uint32 cr;
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291 } hal_jmp_buf_t;
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292
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293 #define CYGARC_JMP_BUF_SIZE (sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32))
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294
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295 typedef cyg_uint32 hal_jmp_buf[ CYGARC_JMP_BUF_SIZE ];
0
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296
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297 externC int hal_setjmp(hal_jmp_buf env);
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298 externC void hal_longjmp(hal_jmp_buf env, int val);
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299
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300 //-----------------------------------------------------------------------------
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301 // Idle thread code.
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302 // This macro is called in the idle thread loop, and gives the HAL the
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303 // chance to insert code. Typical idle thread behaviour might be to halt the
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304 // processor.
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305
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306 externC void hal_idle_thread_action(cyg_uint32 loop_count);
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307
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308 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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309
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310 //-----------------------------------------------------------------------------
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311 // Minimal and sensible stack sizes: the intention is that applications
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312 // will use these to provide a stack size in the first instance prior to
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313 // proper analysis. Idle thread stack should be this big.
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314
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315 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
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316 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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317 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
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318
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319 // This is not a config option because it should not be adjusted except
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320 // under "enough rope" sort of disclaimers.
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321
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322 // Stack frame overhead per call. The PPC ABI defines regs 13..31 as callee
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323 // saved. callee saved variables are irrelevant for us as they would contain
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324 // automatic variables, so we only count the caller-saved regs here
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325 // So that makes r0..r12 + cr, xer, lr, ctr:
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326 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 17)
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327
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328 // Stack needed for a context switch
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329 #define CYGNUM_HAL_STACK_CONTEXT_SIZE \
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330 (38*4 /* offsetof(HAL_SavedRegisters, context_size) */)
2
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331
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332 // Interrupt + call to ISR, interrupt_end() and the DSR
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333 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
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334 ((43*4 /* sizeof(HAL_SavedRegisters) */) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
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335
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336 // We have lots of registers so no particular amount is added in for
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337 // typical local variable usage.
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338
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339 // We define a minimum stack size as the minimum any thread could ever
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340 // legitimately get away with. We can throw asserts if users ask for less
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341 // than this. Allow enough for three interrupt sources - clock, serial and
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342 // one other
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343
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344 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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345
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346 // An interrupt stack which is large enough for all possible interrupt
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347 // conditions (and only used for that purpose) exists. "User" stacks
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348 // can therefore be much smaller
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349
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350 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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351 (16*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
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352
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353 #else
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354
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355 // No separate interrupt stack exists. Make sure all threads contain
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356 // a stack sufficiently large
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357 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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358 (((2+3)*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \
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359 (16*CYGNUM_HAL_STACK_FRAME_SIZE))
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360 #endif
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361
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362 // Now make a reasonable choice for a typical thread size. Pluck figures
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363 // from thin air and say 30 call frames with an average of 16 words of
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364 // automatic variables per call frame
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365 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \
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366 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
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367 30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))
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368
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369 //--------------------------------------------------------------------------
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370 // Macros for switching context between two eCos instances (jump from
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371 // code in ROM to code in RAM or vice versa).
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372
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373 // Should be defined like for MIPS, saving/restoring R2 - but is it
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374 // actually used? I've never seen app code use R2. Something to investigate.
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375 #define CYGARC_HAL_SAVE_GP()
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376 #define CYGARC_HAL_RESTORE_GP()
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377
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378 //-----------------------------------------------------------------------------
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379 #endif // CYGONCE_HAL_ARCH_H
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380 // End of hal_arch.h