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annotate packages/hal/sh/sh3/current/include/var_cache.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL variant cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): jskov
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47 // Contributors:jskov
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48 // Date: 1999-04-23
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <pkgconf/system.h>
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62 #include <pkgconf/hal.h>
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63 #include <cyg/infra/cyg_type.h>
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64 #include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros
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65
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66 #include <cyg/hal/plf_cache.h> // Platform cache definitions
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67
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68 #include CYGBLD_HAL_CPU_MODULES_H // cache module specs
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69
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70 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
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71
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72 //-----------------------------------------------------------------------------
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73 // Cache dimensions - one unified cache
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74
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75 #define HAL_CACHE_UNIFIED
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76
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77 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
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78 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
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79 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
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80
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81 // Cache addressing information
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82 #define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE
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83 #define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP
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84 #define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP
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85
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86 // Writing this to a cache address entry forces a flush of the line if
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87 // it is dirty.
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88 #define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH
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89
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90 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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91
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92 //-----------------------------------------------------------------------------
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93 // Global control of cache
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94
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95 // This is all handled in assembly (see variant.S) due to a requirement about
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96 // not fiddling the cache from cachable memory.
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97
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98 externC void cyg_hal_cache_enable(void);
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99 externC void cyg_hal_cache_disable(void);
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100 externC void cyg_hal_cache_invalidate_all(void);
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101 externC void cyg_hal_cache_sync(void);
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102 externC void cyg_hal_cache_sync_region(cyg_haladdress base,
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103 cyg_haladdrword len);
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104 externC void cyg_hal_cache_write_mode(int mode);
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105
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106 // Enable the cache
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107 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
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108
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109 // Disable the cache
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110 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
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111
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112 // Invalidate the entire cache
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113 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
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114
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115 // Synchronize the contents of the cache with memory.
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116 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
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117
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118 // Query the state of the cache (does not affect the caching)
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119 #define HAL_UCACHE_IS_ENABLED(_state_) \
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120 CYG_MACRO_START \
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121 cyg_uint32 _tmp; \
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122 HAL_READ_UINT32(CYGARC_REG_CCR, _tmp); \
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123 (_state_) = (_tmp & CYGARC_REG_CCR_CE) ? 1 : 0; \
134
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124 CYG_MACRO_END
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125
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126 // Set the cache refill burst size
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127 //#define HAL_UCACHE_BURST_SIZE(_size_)
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128
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129 // Set the cache write mode
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130 #define HAL_UCACHE_WRITE_MODE( _mode_ ) \
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131 CYG_MACRO_START \
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132 cyg_uint32 _m_; \
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133 if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \
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134 _m_ = CYGARC_REG_CCR_WT; \
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135 else \
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136 _m_ = CYGARC_REG_CCR_CB; \
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137 cyg_hal_cache_write_mode(_m_); \
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138 CYG_MACRO_END
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139
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140 #define HAL_UCACHE_WRITETHRU_MODE 0
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141 #define HAL_UCACHE_WRITEBACK_MODE 1
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142
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143 // This macro allows the client to specify separate modes for the two
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144 // regions.
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145 #define HAL_UCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_cache_write_mode(_mode_)
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146
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147 // Load the contents of the given address range into the cache
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148 // and then lock the cache so that it stays there.
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149 //#define HAL_UCACHE_LOCK(_base_, _size_)
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150
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151 // Undo a previous lock operation
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152 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
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153
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154 // Unlock entire cache
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155 //#define HAL_UCACHE_UNLOCK_ALL()
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156
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157 //-----------------------------------------------------------------------------
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158 // Cache line control
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159
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160 // Allocate cache lines for the given address range without reading its
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161 // contents from memory.
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162 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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163
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164 // Write dirty cache lines to memory and invalidate the cache entries
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165 // for the given address range.
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166 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) \
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167 cyg_hal_cache_sync_region((cyg_haladdress) _base_, (cyg_haladdrword)_size_)
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168
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169 // Invalidate cache lines in the given range without writing to memory.
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170 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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171
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172 // Write dirty cache lines to memory for the given address range.
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173 //#define HAL_UCACHE_STORE( _base_ , _size_ )
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174
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175
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176 // Preread the given range into the cache with the intention of reading
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177 // from it later.
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178 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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179
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180 // Preread the given range into the cache with the intention of writing
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181 // to it later.
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182 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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183
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184 // Allocate and zero the cache lines associated with the given range.
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185 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
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186
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187
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188 //-----------------------------------------------------------------------------
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189 // Data and instruction cache macros map onto the both-cache macros
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190
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191 //-----------------------------------------------------------------------------
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192 // Global control of data cache
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193
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194 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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195 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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196 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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197 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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198
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199 // Enable the data cache
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200 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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201
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202 // Disable the data cache
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203 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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204
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205 // Invalidate the entire cache
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206 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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207
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208 // Synchronize the contents of the cache with memory.
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209 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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210
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211 // Query the state of the data cache
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212 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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213
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214 // Set the data cache refill burst size
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215 //#define HAL_DCACHE_BURST_SIZE(_size_)
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216
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217 // Set the data cache write mode
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218 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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219
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220 //#define HAL_DCACHE_WRITETHRU_MODE 0
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221 //#define HAL_DCACHE_WRITEBACK_MODE 1
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222
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223 // Load the contents of the given address range into the data cache
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224 // and then lock the cache so that it stays there.
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225 //#define HAL_DCACHE_LOCK(_base_, _size_)
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226
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227 // Undo a previous lock operation
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228 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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229
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230 // Unlock entire cache
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231 //#define HAL_DCACHE_UNLOCK_ALL()
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232
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233 //-----------------------------------------------------------------------------
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234 // Data cache line control
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235
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236 // Allocate cache lines for the given address range without reading its
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237 // contents from memory.
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238 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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239
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240 // Write dirty cache lines to memory and invalidate the cache entries
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241 // for the given address range.
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242 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ )
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243
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244 // Invalidate cache lines in the given range without writing to memory.
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245 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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246
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247 // Write dirty cache lines to memory for the given address range.
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248 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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249
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250 // Preread the given range into the cache with the intention of reading
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251 // from it later.
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252 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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253
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254 // Preread the given range into the cache with the intention of writing
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255 // to it later.
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256 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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257
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258 // Allocate and zero the cache lines associated with the given range.
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259 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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260
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261 //-----------------------------------------------------------------------------
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262 // Global control of Instruction cache
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263
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264 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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265 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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266 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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267 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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268
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269 // Enable the instruction cache
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270 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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271
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272 // Disable the instruction cache
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273 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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274
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275 // Invalidate the entire cache
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276 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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277
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278
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279 // Synchronize the contents of the cache with memory.
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280 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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281
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282 // Query the state of the instruction cache
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283 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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284
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285 // Set the instruction cache refill burst size
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286 //#define HAL_ICACHE_BURST_SIZE(_size_)
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287
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288 // Load the contents of the given address range into the instruction cache
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289 // and then lock the cache so that it stays there.
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290
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291 //#define HAL_ICACHE_LOCK(_base_, _size_)
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292
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293 // Undo a previous lock operation
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294 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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295
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296 // Unlock entire cache
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297 //#define HAL_ICACHE_UNLOCK_ALL()
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298
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299 //-----------------------------------------------------------------------------
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300 // Instruction cache line control
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301
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302 // Invalidate cache lines in the given range without writing to memory.
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303 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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304
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305 //-----------------------------------------------------------------------------
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306 #endif // ifndef CYGONCE_VAR_CACHE_H
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307 // End of var_cache.h