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annotate packages/hal/synth/i386linux/current/include/var_arch.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 #ifndef CYGONCE_HAL_VAR_ARCH_H
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2 #define CYGONCE_HAL_VAR_ARCH_H
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3
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4 //=============================================================================
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5 //
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6 // var_arch.h
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7 //
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8 // Per-processor information such as processor save states.
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): proven
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47 // Contributors:proven, pjo, nickg,bartv
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48 // Date: 1998-10-05
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49 // Purpose: Define architecture abstractions
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50 // Usage: #include <cyg/hal/hal_arch.h>
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51 //
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52 //####DESCRIPTIONEND####
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53 //
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54 //=============================================================================
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55
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56
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57 #include <cyg/infra/cyg_type.h>
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58
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59 //-----------------------------------------------------------------------------
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60 // Processor saved states. This structure is also defined in arch.inc for
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61 // assembly code. Do not change this without changing that (or vice versa).
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62 // Note: there is no need to worry about floating point contexts, see context.S
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63
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64 typedef struct
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65 {
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66 cyg_uint32 esp;
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67 cyg_uint32 next_context; // only used when dropping through...
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68 cyg_uint32 ebp; // ...from switch_ to load_context
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69 cyg_uint32 ebx;
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70 cyg_uint32 esi;
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71 cyg_uint32 edi;
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72 cyg_bool interrupts; // Are interrupts enabled for this thread?
161
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73 } HAL_SavedRegisters;
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74
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75
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76 //-----------------------------------------------------------------------------
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77 // Bit manipulation routines. These are provided by the processor variant
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78 // HAL to allow for processor-specific implementations.
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79
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80 #define HAL_LSBIT_INDEX(index, mask) \
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81 CYG_MACRO_START \
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82 asm volatile( "bsfl %1,%0\n" \
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83 : "=r" (index) \
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84 : "r" (mask) \
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85 ); \
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86 CYG_MACRO_END
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87
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88 #define HAL_MSBIT_INDEX(index, mask) \
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89 CYG_MACRO_START \
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90 asm volatile( "bsrl %1,%0\n" \
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91 : "=r" (index) \
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92 : "r" (mask) \
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93 ); \
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94 CYG_MACRO_END
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95
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96 //-----------------------------------------------------------------------------
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97 // Context Initialization
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98 // Initialize the context of a thread.
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99 // Arguments:
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100 // _sp_ name of variable containing current sp, will be written with new sp
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101 // _thread_ thread object address, passed as argument to entry point
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102 // _entry_ entry point address.
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103 // _id_ bit pattern used in initializing registers, for debugging.
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104
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105 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
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106 CYG_MACRO_START \
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107 register CYG_WORD* _sp_ = ((CYG_WORD*)((_sparg_) &~15)); \
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108 register HAL_SavedRegisters *_regs_; \
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109 \
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110 /* The 'ret' executed at the end of hal_thread_load_context will */ \
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111 /* use the last entry on the stack as a return pointer (_entry_). */ \
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112 /* Cyg_HardwareThread::thread_entry expects one argument at stack */ \
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113 /* offset 4 (_thread_). The (0xDEADBEEF) entry is the return addr */ \
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114 /* for thread_entry (which is never used). */ \
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115 *(--_sp_) = (CYG_WORD)(0); \
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116 *(--_sp_) = (CYG_WORD)(0); \
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117 *(--_sp_) = (CYG_WORD)(0); \
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118 *(--_sp_) = (CYG_WORD)(0); \
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119 *(--_sp_) = (CYG_WORD)(_thread_); \
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120 *(--_sp_) = (CYG_WORD)(0); \
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121 *(--_sp_) = (CYG_WORD)(_entry_); \
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122 \
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123 _regs_ = (HAL_SavedRegisters *) \
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124 ((unsigned long)_sp_ - sizeof(HAL_SavedRegisters)); \
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125 _regs_->esp = (CYG_WORD) _sp_; \
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126 _regs_->ebx = (CYG_WORD)(_id_); \
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127 _regs_->ebp = (CYG_WORD)(_id_); \
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128 _regs_->esi = (CYG_WORD)(_id_); \
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129 _regs_->edi = (CYG_WORD)(_id_); \
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130 _regs_->interrupts = true; \
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131 (_sparg_) = (CYG_ADDRESS) _regs_; \
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132 CYG_MACRO_END
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133
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134 //-----------------------------------------------------------------------------
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135 // Context switch macros.
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136 // The arguments are pointers to locations where the stack pointer
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137 // of the current thread is to be stored, and from where the sp of the
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138 // next thread is to be fetched.
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139
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140 externC void hal_thread_switch_context( CYG_ADDRESS _to_, CYG_ADDRESS _from_ );
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141 externC void hal_thread_load_context( CYG_ADDRESS _to_ )
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142 __attribute__ ((noreturn));
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143
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144 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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145 hal_thread_switch_context((CYG_ADDRESS)_tspptr_,(CYG_ADDRESS)_fspptr_);
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146
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147 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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148 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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149
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150 //-----------------------------------------------------------------------------
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151 // HAL setjmp
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152
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153 #define CYGARC_JMP_BUF_SP 0
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154 #define CYGARC_JMP_BUF_EBP 1
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155 #define CYGARC_JMP_BUF_EBX 2
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156 #define CYGARC_JMP_BUF_ESI 3
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157 #define CYGARC_JMP_BUF_EDI 4
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158 #define CYGARC_JMP_BUF_PC 5
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159
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160 #define CYGARC_JMP_BUF_SIZE 6
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161
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162 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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163
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164 externC int hal_setjmp(hal_jmp_buf env);
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165 externC void hal_longjmp(hal_jmp_buf env, int val);
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166
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167 //-----------------------------------------------------------------------------
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168 // Minimal and sensible stack sizes: the intention is that applications
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169 // will use these to provide a stack size in the first instance prior to
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170 // proper analysis. Idle thread stack should be this big.
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171
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172 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
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173 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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174 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
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175
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176 // This is not a config option because it should not be adjusted except
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177 // under "enough rope" sort of disclaimers.
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178
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179 // Stack frame overhead per call. 3 local registers (edi, esi, ebx) and
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180 // return address.
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181 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 4)
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182
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183 // Stack needed for a context switch (i386reg_context_size from i386.inc)
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184 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 24)
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185
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186 // Interrupt stack size. Interrupts are handled by signals so the relevant
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187 // data is MINSIGSTKSIZE (see man sigaltstack) or 2048. Given the
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188 // multiplier *15 for STACK_SIZE_MINIMUM, this should be adequate.
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189 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE 2048
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190
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191 // We define a minimum stack size as the minimum any thread could ever
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192 // legitimately get away with. We can throw asserts if users ask for less
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193 // than this. Allow enough for three interrupt sources - clock, serial and
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194 // one other
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195 //
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196 // On the synthetic target memory is cheap so comparatively large stacks
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197 // are possible. This avoids stack overflow problems when working with
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198 // the synthetic target, although arguably the problem is now deferred to
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199 // when the application is moved to real hardware where it will be more
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200 // difficult to track down.
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201 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (16 * 1024)
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202 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (32 * 1024)
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203
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204 //--------------------------------------------------------------------------
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205 // Macros for switching context between two eCos instances (jump from
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206 // code in ROM to code in RAM or vice versa).
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207 #define CYGARC_HAL_SAVE_GP()
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208 #define CYGARC_HAL_RESTORE_GP()
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209
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210 //--------------------------------------------------------------------------
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211 #endif // CYGONCE_HAL_VAR_ARCH_H
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212 // End of var_arch.h