Mercurial > flash_v2

annotate packages/hal/mips/arch/current/include/mips.inc @ 6:d376b777e2ce ecos-sw-1999-05-14

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Merge from eCos master repository on 1999-05-14-19:27:43-BST
author jlarmour
date Fri, 14 May 1999 12:20:00 +0000
parents 443894e2e912
children 306eee292492
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1 #ifndef CYGONCE_HAL_MIPS_INC
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2 #define CYGONCE_HAL_MIPS_INC
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3
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4 ##=============================================================================
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5 ##
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6 ## mips.inc
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7 ##
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8 ## MIPS assembler header file
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9 ##
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10 ##=============================================================================
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11 #####COPYRIGHTBEGIN####
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12 #
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13 # -------------------------------------------
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14 # The contents of this file are subject to the Cygnus eCos Public License
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15 # Version 1.0 (the "License"); you may not use this file except in
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16 # compliance with the License. You may obtain a copy of the License at
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17 # http://sourceware.cygnus.com/ecos
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18 #
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19 # Software distributed under the License is distributed on an "AS IS"
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20 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 # License for the specific language governing rights and limitations under
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22 # the License.
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23 #
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24 # The Original Code is eCos - Embedded Cygnus Operating System, released
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25 # September 30, 1998.
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26 #
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27 # The Initial Developer of the Original Code is Cygnus. Portions created
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28 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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29 # -------------------------------------------
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30 #
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31 #####COPYRIGHTEND####
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32 ##=============================================================================
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33 #######DESCRIPTIONBEGIN####
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34 ##
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35 ## Author(s): nickg
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36 ## Contributors: nickg
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37 ## Date: 1997-10-16
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38 ## Purpose: MIPS definitions.
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39 ## Description: This file contains various definitions and macros that are
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40 ## useful for writing assembly code for the MIPS CPU family.
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41 ## Usage:
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42 ## #include <cyg/hal/mips.inc>
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43 ## ...
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44 ##
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45 ##
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46 ######DESCRIPTIONEND####
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47 ##
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48 ##=============================================================================
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49
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50 ##-----------------------------------------------------------------------------
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51 ## Standard MIPS register names:
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52
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53 #define zero $0
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54 #define z0 $0
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55 #define v0 $2
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56 #define v1 $3
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57 #define a0 $4
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58 #define a1 $5
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59 #define a2 $6
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60 #define a3 $7
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61 #define t0 $8
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62 #define t1 $9
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63 #define t2 $10
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64 #define t3 $11
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65 #define t4 $12
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66 #define t5 $13
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67 #define t6 $14
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68 #define t7 $15
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69 #define s0 $16
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70 #define s1 $17
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71 #define s2 $18
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72 #define s3 $19
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73 #define s4 $20
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74 #define s5 $21
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75 #define s6 $22
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76 #define s7 $23
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77 #define t8 $24
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78 #define t9 $25
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79 #define k0 $26 /* kernel private register 0 */
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80 #define k1 $27 /* kernel private register 1 */
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81 #define gp $28 /* global data pointer */
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82 #define sp $29 /* stack-pointer */
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83 #define fp $30 /* frame-pointer */
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84 #define ra $31 /* return address */
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85 #define pc $pc /* pc, used on mips16 */
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86
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87 #define f0 $f0
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88 #define f1 $f1
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89 #define f2 $f2
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90 #define f3 $f3
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91 #define f4 $f4
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92 #define f5 $f5
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93 #define f6 $f6
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94 #define f7 $f7
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95 #define f8 $f8
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96 #define f9 $f9
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97 #define f10 $f10
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98 #define f11 $f11
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99 #define f12 $f12
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100 #define f13 $f13
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101 #define f14 $f14
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102 #define f15 $f15
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103 #define f16 $f16
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104 #define f17 $f17
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105 #define f18 $f18
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106 #define f19 $f19
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107 #define f20 $f20
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108 #define f21 $f21
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109 #define f22 $f22
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110 #define f23 $f23
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111 #define f24 $f24
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112 #define f25 $f25
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113 #define f26 $f26
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114 #define f27 $f27
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115 #define f28 $f28
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116 #define f29 $f29
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117 #define f30 $f30
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118 #define f31 $f31
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119
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120 // Coprocessor 0 registers
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121
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122 #define index $0 // TLB entry index register
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123 #define random $1 // TLB random index register
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124 #define tlblo0 $2 // TLB even page entry register
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125 #define tlblo1 $3 // TLB odd page entry register
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126 #define config $3 // Configuration register (TX39 only)
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127 #define context $4 // TLB context register
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128 #define pagemask $5 // TLB page size mask
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129 #define wired $6 // TLB wired boundary
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130 #define cache $7 // Cache control
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131 #define badvr $8 // Bad virtual address
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132 #define count $9 // Timer cycle count register
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133 #define tlbhi $10 // TLB virtual address match register
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134 #define compare $11 // Timer compare register
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135 #define status $12 // Status register
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136 #define cause $13 // Exception cause
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137 #define epc $14 // Exception pc value
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138 #define prid $15 // processor ID
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139 #define config0 $16 // Config register 0
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140
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141
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142 #------------------------------------------------------------------------------
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143
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144 #define FUNC_START(name) \
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145 .type name,@function; \
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146 .globl name; \
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147 .ent name; \
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148 name:
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149
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150 #define FUNC_END(name) \
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151 name##_end: \
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152 .end name \
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153
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154 #------------------------------------------------------------------------------
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155 #endif // ifndef CYGONCE_HAL_MIPS_INC
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156 # end of mips.inc