Mercurial > flash_v2
annotate packages/hal/mips/arch/current/src/vectors.S @ 6:d376b777e2ce ecos-sw-1999-05-14
Merge from eCos master repository on 1999-05-14-19:27:43-BST
| author | jlarmour |
|---|---|
| date | Fri, 14 May 1999 12:20:00 +0000 |
| parents | 443894e2e912 |
| children | ece80412419a |
| rev | line source |
|---|---|
| 0 | 1 ##============================================================================= |
| 2 ## | |
| 3 ## vectors.S | |
| 4 ## | |
| 5 ## MIPS exception vectors | |
| 6 ## | |
| 7 ##============================================================================= | |
| 8 #####COPYRIGHTBEGIN#### | |
| 9 # | |
| 10 # ------------------------------------------- | |
| 11 # The contents of this file are subject to the Cygnus eCos Public License | |
| 12 # Version 1.0 (the "License"); you may not use this file except in | |
| 13 # compliance with the License. You may obtain a copy of the License at | |
| 14 # http://sourceware.cygnus.com/ecos | |
| 15 # | |
| 16 # Software distributed under the License is distributed on an "AS IS" | |
| 17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 # License for the specific language governing rights and limitations under | |
| 19 # the License. | |
| 20 # | |
| 21 # The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 # September 30, 1998. | |
| 23 # | |
| 24 # The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 26 # ------------------------------------------- |
| 27 # | |
| 28 #####COPYRIGHTEND#### | |
| 29 ##============================================================================= | |
| 30 #######DESCRIPTIONBEGIN#### | |
| 31 ## | |
| 32 ## Author(s): nickg | |
| 33 ## Contributors: nickg | |
| 34 ## Date: 1998-02-04 | |
| 35 ## Purpose: MIPS exception vectors | |
| 36 ## Description: This file defines the code placed into the exception | |
| 37 ## vectors. It also contains the first level default VSRs | |
| 38 ## that save and restore state for both exceptions and | |
| 39 ## interrupts. | |
| 40 ## | |
| 41 ######DESCRIPTIONEND#### | |
| 42 ## | |
| 43 ##============================================================================= | |
| 44 | |
| 45 #include <pkgconf/system.h> | |
| 46 #include <pkgconf/hal.h> | |
| 47 | |
| 48 #ifdef CYGPKG_KERNEL | |
| 49 # include <pkgconf/kernel.h> | |
| 50 #endif | |
| 51 | |
|
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52 #include <cyg/hal/arch.inc> |
| 0 | 53 |
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54 .extern cyg_instrument |
| 2 | 55 |
| 0 | 56 ##----------------------------------------------------------------------------- |
| 57 ## Hardware supplied vectors | |
| 58 | |
| 59 .set noreorder | |
| 60 .set noat | |
| 61 | |
| 62 .section ".reset_vector","ax" | |
| 63 | |
| 64 # Reset vector at 0xBFC00000 | |
| 65 | |
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66 FUNC_START(reset_vector) |
| 0 | 67 la v0,_start # jump to start |
| 68 jr v0 | |
| 69 nop # (delay slot) | |
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70 FUNC_END(reset_vector) |
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71 |
| 0 | 72 .section ".debug_vector","ax" |
| 73 | |
| 74 # Debug vector at 0xBFC00200 | |
| 75 | |
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76 FUNC_START(debug_vector) |
| 0 | 77 la k0,32 |
| 78 la k1,hal_vsr_table # Get VSR table | |
| 79 lw k1,32*4(k1) # load debug vector | |
| 80 jr k1 # go there | |
| 81 nop # (delay slot) | |
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82 FUNC_END(debug_vector) |
| 0 | 83 |
| 84 .section ".other_vector","ax" | |
| 85 | |
| 86 # Common vector at 0x80000080 or 0xBFC00180 | |
| 87 | |
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88 FUNC_START(other_vector) |
| 0 | 89 mfc0 k0,cause # K0 = exception cause |
| 90 nop | |
| 91 andi k0,k0,0x7F # isolate exception code | |
| 92 la k1,hal_vsr_table # address of VSR table | |
| 93 add k1,k1,k0 # offset of VSR entry | |
| 94 lw k1,0(k1) # k1 = pointer to VSR | |
| 95 jr k1 # go there | |
| 96 nop # (delay slot) | |
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97 FUNC_END(other_vector) |
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98 |
| 0 | 99 .section ".utlb_vector","ax" |
| 100 | |
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101 FUNC_START(utlb_vector) |
| 0 | 102 la k0,33 |
| 103 la k1,hal_vsr_table # Get VSR table | |
| 104 lw k1,33*4(k1) # load utlb vector | |
| 105 jr k1 # go there | |
| 106 nop # (delay slot) | |
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107 FUNC_END(utlb_vector) |
| 0 | 108 |
| 109 ##----------------------------------------------------------------------------- | |
| 110 ## Startup code | |
| 111 | |
| 112 .text | |
| 113 | |
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114 FUNC_START(_start) |
| 0 | 115 |
| 116 # Initialize hardware | |
| 117 | |
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118 hal_cpu_init |
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119 hal_mmu_init |
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120 hal_fpu_init |
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121 hal_memc_init |
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122 hal_intc_init |
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123 hal_cache_init |
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124 hal_diag_init |
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125 hal_timer_init |
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126 |
| 0 | 127 # Load Global Pointer register. |
| 128 la gp,_gp | |
| 129 | |
| 130 # load initial stack pointer | |
| 131 la a0,__interrupt_stack | |
| 132 move sp,a0 | |
| 133 | |
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134 hal_mon_init |
| 0 | 135 |
| 136 #ifdef CYG_HAL_STARTUP_ROM | |
| 137 # Copy data from ROM to RAM | |
| 138 | |
| 139 .extern hal_copy_data | |
| 140 jal hal_copy_data | |
| 141 nop | |
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142 |
| 0 | 143 #endif |
| 144 | |
| 145 # Zero BSS | |
| 146 | |
| 147 .extern hal_zero_bss | |
| 148 jal hal_zero_bss | |
| 149 nop | |
| 150 | |
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151 # Cal variant and platform HAL |
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152 # initialization routines. |
| 0 | 153 |
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154 .extern hal_variant_init |
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155 jal hal_variant_init |
| 2 | 156 nop |
| 157 | |
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158 .extern hal_platform_init |
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159 jal hal_platform_init |
| 2 | 160 nop |
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161 |
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162 # Call constructors |
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163 .extern cyg_hal_invoke_constructors |
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164 jal cyg_hal_invoke_constructors |
| 2 | 165 nop |
| 166 | |
| 167 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 168 .extern initialize_stub | |
| 169 jal initialize_stub | |
| 0 | 170 nop |
| 2 | 171 #endif |
| 0 | 172 |
| 173 # Call cyg_start | |
| 174 | |
| 175 .extern cyg_start | |
| 176 jal cyg_start | |
| 177 nop | |
| 178 | |
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179 9: j 9b # Loop if we return |
| 0 | 180 nop # (delay slot) |
| 181 | |
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182 FUNC_END(_start ) |
| 0 | 183 |
| 184 ##----------------------------------------------------------------------------- | |
| 185 ## Default exception VSR. | |
| 186 ## Saves machine state and calls external handling code. | |
| 187 | |
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188 FUNC_START(__default_exception_vsr) |
| 0 | 189 |
| 190 # We enter here with all of the CPU state still | |
| 191 # in its registers except: | |
| 192 # K0 = vector index | |
| 193 # K1 = address of this function | |
| 194 | |
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195 |
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196 move k1,sp # K1 = original SP |
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197 |
| 0 | 198 #ifdef CYG_HAL_ROM_MONITOR |
| 199 # Switch to interrupt stack to handle exception | |
| 200 la sp,__interrupt_stack | |
| 201 #endif | |
| 202 | |
| 203 addi sp,sp,-mips_exception_decrement | |
| 204 # space for registers + safety margin | |
| 205 | |
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206 mfc0 k0,cause |
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207 andi k0,k0,0x7F # isolate exception code |
| 0 | 208 sw k0,mipsreg_vector(sp) # store vector |
| 209 | |
| 210 .set noat | |
| 211 # store GPRs | |
| 212 sw $0,(mipsreg_regs+0*4)(sp) | |
| 213 sw $1,(mipsreg_regs+1*4)(sp) | |
| 214 sw $2,(mipsreg_regs+2*4)(sp) | |
| 215 sw $3,(mipsreg_regs+3*4)(sp) | |
| 216 sw $4,(mipsreg_regs+4*4)(sp) | |
| 217 sw $5,(mipsreg_regs+5*4)(sp) | |
| 218 sw $6,(mipsreg_regs+6*4)(sp) | |
| 219 sw $7,(mipsreg_regs+7*4)(sp) | |
| 220 sw $8,(mipsreg_regs+8*4)(sp) | |
| 221 sw $9,(mipsreg_regs+9*4)(sp) | |
| 222 sw $10,(mipsreg_regs+10*4)(sp) | |
| 223 sw $11,(mipsreg_regs+11*4)(sp) | |
| 224 sw $12,(mipsreg_regs+12*4)(sp) | |
| 225 sw $13,(mipsreg_regs+13*4)(sp) | |
| 226 sw $14,(mipsreg_regs+14*4)(sp) | |
| 227 sw $15,(mipsreg_regs+15*4)(sp) | |
| 228 sw $16,(mipsreg_regs+16*4)(sp) | |
| 229 sw $17,(mipsreg_regs+17*4)(sp) | |
| 230 sw $18,(mipsreg_regs+18*4)(sp) | |
| 231 sw $19,(mipsreg_regs+19*4)(sp) | |
| 232 sw $20,(mipsreg_regs+20*4)(sp) | |
| 233 sw $21,(mipsreg_regs+21*4)(sp) | |
| 234 sw $22,(mipsreg_regs+22*4)(sp) | |
| 235 sw $23,(mipsreg_regs+23*4)(sp) | |
| 236 sw $24,(mipsreg_regs+24*4)(sp) | |
| 237 sw $25,(mipsreg_regs+25*4)(sp) | |
| 238 # sw $26,(mipsreg_regs+26*4)(sp) # == K0 | |
| 239 # sw $27,(mipsreg_regs+27*4)(sp) # == K1 | |
| 240 sw $28,(mipsreg_regs+28*4)(sp) # == GP | |
| 241 # sw $29,(mipsreg_regs+29*4)(sp) # == SP | |
| 242 sw $30,(mipsreg_regs+30*4)(sp) # == FP | |
| 243 sw $31,(mipsreg_regs+31*4)(sp) # == RA | |
| 244 | |
| 245 mfhi a0 | |
| 246 mflo a1 | |
| 247 sw a0,mipsreg_hi(sp) | |
| 248 sw a1,mipsreg_lo(sp) | |
| 249 | |
| 250 # K1 contains original SP | |
| 251 sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump | |
| 252 | |
| 253 # save remaining machine state registers | |
| 254 mfc0 t0,cause | |
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255 mfc0 t1,status |
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256 mfc0 t2,cache |
| 0 | 257 mfc0 t3,badvr |
| 258 mfc0 t4,config | |
| 259 mfc0 t5,prid | |
| 260 mfc0 t6,epc | |
| 261 | |
| 262 sw t0,mipsreg_cause(sp) | |
| 263 sw t1,mipsreg_sr(sp) | |
| 264 sw t2,mipsreg_cache(sp) | |
| 265 sw t3,mipsreg_badvr(sp) | |
| 266 sw t4,mipsreg_config(sp) | |
| 267 sw t5,mipsreg_prid(sp) | |
| 268 sw t6,mipsreg_pc(sp) | |
| 269 | |
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270 hal_fpu_save sp |
| 0 | 271 |
| 272 # The machine state is now all saved on the stack. | |
| 273 | |
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274 hal_diag_excpt_start |
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275 |
| 0 | 276 # Load Global Pointer register. |
| 277 la gp,_gp | |
| 278 | |
| 279 move s0,sp # save pointer to saved state | |
| 280 | |
| 281 addi sp,sp,-mips_stack_frame_size # make a null frame | |
| 282 | |
| 283 # Need to set up back pointers etc. ??? | |
| 284 | |
| 285 la ra,restore_state # load return address | |
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286 |
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287 hal_cpu_except_enable # reenable exceptions |
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288 |
| 0 | 289 .extern exception_handler |
| 290 j exception_handler # call C code | |
| 291 move a0,s0 # arg0 = register dump (delay slot) | |
| 292 | |
| 293 # When the exception handler returns, it will | |
| 294 # go back to restore_state, below. | |
| 295 | |
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296 FUNC_END(__default_exception_vsr) |
| 0 | 297 |
| 298 ##------------------------------------------------------------------------------ | |
| 299 ## Default interrupt VSR. | |
| 300 ## Saves machine state and calls appropriate ISR. When done, calls | |
| 301 ## interrupt_end() to finish up and possibly reschedule. | |
| 302 | |
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303 FUNC_START(__default_interrupt_vsr) |
| 0 | 304 |
| 305 | |
| 306 # We enter here with all of the CPU state still | |
| 307 # in its registers except: | |
| 308 # K0 = vector index | |
| 309 # K1 = address of this function | |
| 310 | |
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311 move k1,sp # K1 = original SP |
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312 |
| 0 | 313 addi sp,sp,-mips_exception_decrement |
| 314 # space for registers + safety margin | |
| 315 | |
| 316 sw k0,mipsreg_vector(sp) # store vector | |
| 317 | |
| 318 # store GPRs | |
| 319 sw $0,(mipsreg_regs+0*4)(sp) | |
| 320 sw $1,(mipsreg_regs+1*4)(sp) | |
| 321 sw $2,(mipsreg_regs+2*4)(sp) | |
| 322 sw $3,(mipsreg_regs+3*4)(sp) | |
| 323 sw $4,(mipsreg_regs+4*4)(sp) | |
| 324 sw $5,(mipsreg_regs+5*4)(sp) | |
| 325 sw $6,(mipsreg_regs+6*4)(sp) | |
| 326 sw $7,(mipsreg_regs+7*4)(sp) | |
| 327 sw $8,(mipsreg_regs+8*4)(sp) | |
| 328 sw $9,(mipsreg_regs+9*4)(sp) | |
| 329 sw $10,(mipsreg_regs+10*4)(sp) | |
| 330 sw $11,(mipsreg_regs+11*4)(sp) | |
| 331 sw $12,(mipsreg_regs+12*4)(sp) | |
| 332 sw $13,(mipsreg_regs+13*4)(sp) | |
| 333 sw $14,(mipsreg_regs+14*4)(sp) | |
| 334 sw $15,(mipsreg_regs+15*4)(sp) | |
| 335 sw $16,(mipsreg_regs+16*4)(sp) | |
| 336 sw $17,(mipsreg_regs+17*4)(sp) | |
| 337 sw $18,(mipsreg_regs+18*4)(sp) | |
| 338 sw $19,(mipsreg_regs+19*4)(sp) | |
| 339 sw $20,(mipsreg_regs+20*4)(sp) | |
| 340 sw $21,(mipsreg_regs+21*4)(sp) | |
| 341 sw $22,(mipsreg_regs+22*4)(sp) | |
| 342 sw $23,(mipsreg_regs+23*4)(sp) | |
| 343 sw $24,(mipsreg_regs+24*4)(sp) | |
| 344 sw $25,(mipsreg_regs+25*4)(sp) | |
| 345 # sw $26,(mipsreg_regs+26*4)(sp) # == K0 | |
| 346 # sw $27,(mipsreg_regs+27*4)(sp) # == K1 | |
| 347 sw $28,(mipsreg_regs+28*4)(sp) # == GP | |
| 348 # sw $29,(mipsreg_regs+29*4)(sp) # == SP | |
| 349 sw $30,(mipsreg_regs+30*4)(sp) # == FP | |
| 350 sw $31,(mipsreg_regs+31*4)(sp) # == RA | |
| 351 | |
| 352 mfhi a0 | |
| 353 mflo a1 | |
| 354 sw a0,mipsreg_hi(sp) | |
| 355 sw a1,mipsreg_lo(sp) | |
| 356 | |
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357 # K1 contains original SP |
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358 sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump |
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359 |
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360 mfc0 t1,status |
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361 mfc0 t2,cache |
| 0 | 362 mfc0 t3,epc |
| 363 | |
| 364 sw t1,mipsreg_sr(sp) | |
| 365 sw t2,mipsreg_cache(sp) | |
| 366 sw t3,mipsreg_pc(sp) | |
| 367 | |
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368 hal_fpu_save sp |
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369 |
| 0 | 370 # The machine state is now all saved on the stack. |
| 371 | |
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372 hal_diag_intr_start |
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373 |
| 0 | 374 # Load Global Pointer register. |
| 375 la gp,_gp | |
| 376 | |
| 377 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 2 | 378 .extern cyg_scheduler_sched_lock |
| 379 la v0,cyg_scheduler_sched_lock | |
| 0 | 380 lw a0,0(v0) |
| 381 addi a0,a0,1 | |
| 382 sw a0,0(v0) | |
| 383 #endif | |
| 384 | |
| 385 move s0,sp # save pointer to saved state | |
| 386 | |
| 387 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 388 | |
| 389 la a0,__interrupt_stack # a0 = stack top | |
| 390 la a1,__interrupt_stack_base # a1 = stack base | |
| 391 sub a3,sp,a1 # a3 = sp - base | |
| 392 bltz a3,1f # if < 0 - not on istack | |
| 393 nop # delay slot | |
| 394 sub t0,a0,sp # t0 = top - sp | |
| 395 bgtz t0,8f # if > 0 - already on istack | |
| 396 nop # delay slot | |
| 397 1: | |
| 398 move sp,a0 # switch to istack | |
| 399 8: | |
| 400 addi sp,sp,-4 # space for old SP | |
| 401 sw s0,0(sp) # save old SP on stack | |
| 402 | |
| 403 #endif | |
| 404 | |
| 405 subu sp,sp,mips_stack_frame_size # make a null frame | |
| 406 | |
| 407 # Need to set up back pointers etc. ??? | |
| 408 | |
| 409 # Decode external interrupt via interrupt controller | |
| 410 | |
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411 hal_intc_decode s2 |
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412 |
| 0 | 413 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN |
| 414 move s1,zero # Just vector zero is supported | |
| 415 #else | |
| 416 move s1,s2 # Vector == interrupt number | |
| 417 #endif | |
| 418 | |
| 419 # Here s1 is the number of the vector to be called and s2 is | |
| 420 # the number of the interrupt being serviced. | |
| 421 | |
| 422 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 423 | |
| 424 # Call cyg_instrument to record that this interrupt is being raised. | |
| 425 | |
| 426 li a0,0x0301 # a0 = type = INTR,RAISE | |
| 427 move a1,s1 # a1 = vector number | |
| 428 jal cyg_instrument # call instrument function | |
| 429 xor a2,a2,a2 # arg2 = 0 (delay slot) | |
| 430 #endif | |
| 431 | |
| 432 sll s1,s1,2 # s1 = byte offset of vector | |
| 433 | |
| 434 la t2,hal_interrupt_handlers # handler table | |
| 435 add t2,t2,s1 # address of ISR ptr | |
| 436 lw t2,0(t2) # ISR pointer | |
| 437 | |
| 438 la a1,hal_interrupt_data # data table | |
| 439 add a1,a1,s1 # address of data ptr | |
| 440 lw a1,0(a1) # Data pointer | |
| 441 | |
| 442 move a0,s2 # pass interrupt number | |
| 2 | 443 |
| 444 move a2,s0 # arg3 = saved register dump | |
| 445 | |
| 0 | 446 jalr t2 # call ISR via t2 |
| 447 nop # (delay slot) | |
| 448 | |
| 449 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 450 | |
| 451 # If we are returning from the last nested interrupt, move back | |
| 452 # to the thread stack. interrupt_end() must be called on the | |
| 453 # thread stack since it potentially causes a context switch. | |
| 454 # Since we have arranged for the top of stack location to | |
| 455 # contain the sp we need to go back to here, just pop it off | |
| 456 # and put it in SP. | |
| 457 | |
| 458 | |
| 459 lw sp,mips_stack_frame_size(sp) # sp = *sp | |
| 460 subu sp,sp,mips_stack_frame_size # make a null frame | |
| 461 #endif | |
| 462 | |
| 463 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 464 | |
| 465 # We only need to call _interrupt_end() when there is a kernel | |
| 466 # present to do any tidying up. | |
| 467 | |
| 468 # On return v0 bit 1 will indicate whether a DSR is | |
| 469 # to be posted. Pass this together with a pointer to | |
| 470 # the interrupt object we have just used to the | |
| 471 # interrupt tidy up routine. | |
| 472 | |
| 473 # Note that s0, s1 and s2 are defined to be preserved across | |
| 474 # calls by the calling convention, so they still contain | |
| 475 # the register dump, the vector offset and the interrupt number | |
| 476 # respectively. | |
| 477 | |
| 478 move a0,v0 # put ISR result in arg0 | |
| 479 | |
| 480 la a1,hal_interrupt_objects # interrupt object table | |
| 481 add a1,a1,s1 # address of object ptr | |
| 482 lw a1,0(a1) # a1 = object ptr | |
| 483 | |
| 484 move a2,s0 # arg3 = saved register dump | |
| 485 | |
| 486 .extern interrupt_end | |
| 487 jal interrupt_end # call into C to finish off | |
| 488 nop # (delay slot) | |
| 489 | |
| 490 #endif | |
| 491 | |
| 492 restore_state: | |
| 493 | |
| 494 # All done, restore CPU state and continue | |
| 495 | |
| 496 addi sp,sp,mips_stack_frame_size # retrieve CPU state ptr | |
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497 |
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498 # Disable interrupts again while we restore state. |
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499 |
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500 hal_diag_restore |
| 0 | 501 |
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502 hal_fpu_load sp |
| 0 | 503 |
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504 lw t0,mipsreg_cache(sp) |
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505 lw t1,mipsreg_hi(sp) |
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506 lw t2,mipsreg_lo(sp) |
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507 |
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508 mtc0 t0,cache |
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509 mthi t1 |
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510 mtlo t2 |
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511 |
| 0 | 512 # load GPRs |
| 513 # lw $0,(mipsreg_regs+0*4)(sp) | |
| 514 lw $1,(mipsreg_regs+1*4)(sp) | |
| 515 lw $2,(mipsreg_regs+2*4)(sp) | |
| 516 lw $3,(mipsreg_regs+3*4)(sp) | |
| 517 lw $4,(mipsreg_regs+4*4)(sp) | |
| 518 lw $5,(mipsreg_regs+5*4)(sp) | |
| 519 lw $6,(mipsreg_regs+6*4)(sp) | |
| 520 lw $7,(mipsreg_regs+7*4)(sp) | |
| 521 lw $8,(mipsreg_regs+8*4)(sp) | |
| 522 lw $9,(mipsreg_regs+9*4)(sp) | |
| 523 lw $10,(mipsreg_regs+10*4)(sp) | |
| 524 lw $11,(mipsreg_regs+11*4)(sp) | |
| 525 lw $12,(mipsreg_regs+12*4)(sp) | |
| 526 lw $13,(mipsreg_regs+13*4)(sp) | |
| 527 lw $14,(mipsreg_regs+14*4)(sp) | |
| 528 lw $15,(mipsreg_regs+15*4)(sp) | |
| 529 lw $16,(mipsreg_regs+16*4)(sp) | |
| 530 lw $17,(mipsreg_regs+17*4)(sp) | |
| 531 lw $18,(mipsreg_regs+18*4)(sp) | |
| 532 lw $19,(mipsreg_regs+19*4)(sp) | |
| 533 lw $20,(mipsreg_regs+20*4)(sp) | |
| 534 lw $21,(mipsreg_regs+21*4)(sp) | |
| 535 lw $22,(mipsreg_regs+22*4)(sp) | |
| 536 lw $23,(mipsreg_regs+23*4)(sp) | |
| 537 lw $24,(mipsreg_regs+24*4)(sp) | |
| 538 lw $25,(mipsreg_regs+25*4)(sp) | |
| 539 # lw $26,(mipsreg_regs+26*4)(sp) # == K0 | |
| 540 # lw $27,(mipsreg_regs+27*4)(sp) # == K1 | |
| 541 lw $28,(mipsreg_regs+28*4)(sp) # == GP | |
| 542 # lw $29,(mipsreg_regs+29*4)(sp) # == SP | |
| 543 lw $30,(mipsreg_regs+30*4)(sp) # == FP | |
| 544 lw $31,(mipsreg_regs+31*4)(sp) # == RA | |
| 545 | |
| 546 lw k0,mipsreg_pc(sp) # K0 = return PC | |
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547 lw k1,mipsreg_sr(sp) # K1 = saved SR |
| 0 | 548 lw sp,(mipsreg_regs+29*4)(sp) # load SP |
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549 |
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550 # Invoke CPU specific mechanism for returning from this |
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551 # exception |
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552 |
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553 hal_cpu_eret k0,k1 |
| 0 | 554 |
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555 FUNC_END(__default_interrupt_vsr) |
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556 |
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557 hal_intc_decode_data |
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558 |
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559 ##----------------------------------------------------------------------------- |
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560 ## Execute pending DSRs on the interrupt stack with interrupts enabled. |
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561 ## Note: this can only be called from code running on a thread stack |
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562 |
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563 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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564 .extern cyg_interrupt_call_pending_DSRs |
| 0 | 565 |
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566 FUNC_START(hal_interrupt_stack_call_pending_DSRs) |
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567 mfc0 t0,status # get status register value |
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568 la v0,__interrupt_stack # v0 = interrupt stack |
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569 move v1,sp # v1 = original stack ptr |
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570 move sp,v0 # sp = interrupt stack |
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571 addi sp,sp,-32 # make a null frame |
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572 sw v1,16(sp) # save old sp |
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573 sw ra,20(sp) # save old ra |
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574 sw t0,24(sp) # save old sr |
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575 |
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576 hal_cpu_int_enable |
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577 |
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578 jal cyg_interrupt_call_pending_DSRs # call back to kernel |
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579 nop |
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580 |
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581 lw a0,24(sp) # get status reg |
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582 |
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583 hal_cpu_int_merge a0 # merge with current SR |
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584 |
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585 lw ra,20(sp) # restore ra |
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586 lw sp,16(sp) # restore sp |
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587 |
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588 jr ra # go back |
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589 nop # delay slot |
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590 |
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591 FUNC_END(hal_interrupt_stack_call_pending_DSRs) |
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592 #endif |
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593 |
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594 |
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595 // Short circuit in case any code tries to use "__gccmain()" |
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596 FUNC_START(__gccmain) |
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597 jr ra |
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598 FUNC_END(__gccmain) |
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599 |
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600 |
| 0 | 601 ##----------------------------------------------------------------------------- |
| 602 ## Interrupt Stack. | |
| 603 ## Used during intialization and for executing ISRs. | |
| 604 | |
| 605 .bss | |
| 606 | |
| 607 .balign 16 | |
| 608 __interrupt_stack_base: | |
| 609 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 610 .byte 0 | |
| 611 .endr | |
| 612 .balign 16 | |
| 613 __interrupt_stack: | |
| 614 | |
| 615 .long 0,0,0,0,0,0,0,0 | |
| 616 | |
| 617 ##----------------------------------------------------------------------------- | |
| 618 ## VSR table. | |
| 619 ## The main interrupt code indirects through here to find the VSR | |
| 620 ## to execute for each architecture defined interrupt. | |
| 621 ## This is only used for simulated targets, on real targets a fixed location VSR | |
| 622 ## table is now allocated at 0x80000100. | |
| 623 | |
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624 #ifndef CYG_HAL_MIPS_VSR_TABLE_DEFINED |
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625 |
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626 ## .section ".vsr_table","a" |
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627 |
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628 .data |
| 0 | 629 |
| 630 .globl hal_vsr_table | |
| 631 | |
| 632 hal_vsr_table: | |
| 633 .long __default_interrupt_vsr | |
| 634 .rept 63 | |
| 635 .long __default_exception_vsr | |
| 636 .endr | |
| 637 | |
| 638 #endif | |
| 639 | |
| 640 #------------------------------------------------------------------------------ | |
| 641 # Interrupt vector tables. | |
| 642 # These tables contain the isr, data and object pointers used to deliver | |
| 643 # interrupts to user code. | |
| 644 # hal_interrupt_level contains the interrupt level set by | |
| 645 # HAL_INTERRUPT_CONFIGURE(). | |
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646 # This is a default set that provide support only for the 6 external |
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647 # interrupts in the status/cause registers. Platforms or boards are expected |
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648 # to define their own versions of these if they have their own interrupt mappings. |
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649 |
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650 #ifndef CYG_HAL_MIPS_ISR_TABLES_DEFINED |
| 0 | 651 |
| 652 .extern hal_default_isr | |
| 653 | |
| 654 .data | |
| 655 | |
| 656 .globl hal_interrupt_handlers | |
| 657 hal_interrupt_handlers: | |
| 658 .long hal_default_isr | |
| 659 .long hal_default_isr | |
| 660 .long hal_default_isr | |
| 661 .long hal_default_isr | |
| 662 .long hal_default_isr | |
| 663 .long hal_default_isr | |
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664 |
| 0 | 665 |
| 666 .globl hal_interrupt_data | |
| 667 hal_interrupt_data: | |
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668 .rept 6 |
| 0 | 669 .long 0 |
| 670 .endr | |
| 671 | |
| 672 .globl hal_interrupt_objects | |
| 673 hal_interrupt_objects: | |
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674 .rept 6 |
| 0 | 675 .long 0 |
| 676 .endr | |
| 677 | |
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678 #endif |
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679 |
| 0 | 680 ##----------------------------------------------------------------------------- |
| 681 ## end of vectors.S | |
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682 |
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683 |
