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annotate packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c @ 1659:e2264d5f9337

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* src/if_cs8900a.c: Drop "ghost" frames with zero length
author jlarmour
date Thu, 27 May 2004 06:48:47 +0000
parents bf994e1a516c
children 67ee34ead3f4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 //==========================================================================
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2 //
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3 // dev/if_cs8900a.c
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4 //
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5 // Device driver for Cirrus Logic CS8900A ethernet controller
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
196
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40 //####BSDCOPYRIGHTBEGIN####
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41 //
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42 // -------------------------------------------
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43 //
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44 // Portions of this software may have been derived from OpenBSD or other sources,
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45 // and are covered by the appropriate copyright disclaimers included herein.
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46 //
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47 // -------------------------------------------
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48 //
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49 //####BSDCOPYRIGHTEND####
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50 //==========================================================================
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51 //#####DESCRIPTIONBEGIN####
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52 //
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53 // Author(s): gthomas
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54 // Contributors: gthomas, jskov
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55 // Date: 2001-11-02
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56 // Purpose:
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57 // Description: Driver for CS8900 ethernet controller
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58 //
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59 // Note: Platform can define CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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60 // to get a timer thread polling instead of interupt based
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61 // operation.
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62 //
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63 // Note: Driver will need some changes to support multiple instances
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64 //
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65 //####DESCRIPTIONEND####
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66 //
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67 //==========================================================================
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68
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69 #include <pkgconf/system.h>
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70 #ifdef CYGPKG_KERNEL
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71 #include <cyg/kernel/kapi.h>
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72 #endif
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73 #include <pkgconf/io_eth_drivers.h>
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ae8511176102 Fix CDL dependencies for stand-alone/system operation.
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74
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75 #include <cyg/infra/cyg_type.h>
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76 #include <cyg/hal/hal_arch.h>
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77 #include <cyg/hal/hal_intr.h>
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78 #include <cyg/hal/hal_endian.h>
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79 #include <cyg/infra/diag.h>
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80 #include <cyg/hal/drv_api.h>
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81 #undef __ECOS
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82 #define __ECOS
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83 #include <cyg/io/eth/eth_drv.h>
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84 #include <cyg/io/eth/netdev.h>
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85
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86 #include <cyg/io/cs8900.h>
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87
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88 #define __WANT_DEVS
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89 #include CYGDAT_DEVS_ETH_CL_CS8900A_INL
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90 #undef __WANT_DEVS
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91
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92 // NOINTS operation only relevant when the NET package is loaded
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93 #if !defined(CYGPKG_NET) || !defined(CYGPKG_KERNEL)
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94 # undef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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95 #endif
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96
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97 #ifdef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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98 #define STACK_SIZE CYGNUM_HAL_STACK_SIZE_MINIMUM
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99 static char cs8900a_fake_int_stack[STACK_SIZE];
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100 static cyg_thread cs8900a_fake_int_thread_data;
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101 static cyg_handle_t cs8900a_fake_int_thread_handle;
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102 static void cs8900a_fake_int(cyg_addrword_t);
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103 #endif
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104
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105 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
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106 extern int cyg_io_eth_net_debug;
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107 #endif
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108
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109 static void cs8900a_poll(struct eth_drv_sc *sc);
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110 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
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111 // This ISR is called when the ethernet interrupt occurs
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112 static int
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113 cs8900a_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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114 {
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115 cs8900a_priv_data_t* cpd = (cs8900a_priv_data_t *)data;
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116 cyg_drv_interrupt_mask(cpd->interrupt);
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117 cyg_drv_interrupt_acknowledge(cpd->interrupt);
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118 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
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119 }
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120
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121 static void
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122 cs8900a_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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123 {
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124 // This conditioning out is necessary because of explicit calls to this
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125 // DSR - which would not ever be called in the case of a polled mode
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126 // usage ie. in RedBoot.
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127 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
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128 cs8900a_priv_data_t* cpd = (cs8900a_priv_data_t *)data;
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129 struct cyg_netdevtab_entry *ndp = (struct cyg_netdevtab_entry *)(cpd->tab);
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130 struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
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131
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132 DEBUG_FUNCTION();
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133
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134 // but here, it must be a *sc:
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135 eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
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136 #else
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137 # ifndef CYGPKG_REDBOOT
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138 # error Empty CS8900A ethernet DSR is compiled. Is this what you want?
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139 # endif
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140 #endif
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141 }
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142 #endif
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143
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144 // The deliver function (ex-DSR) handles the ethernet [logical] processing
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145 static void
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146 cs8900a_deliver(struct eth_drv_sc *sc)
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147 {
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148 cs8900a_poll(sc);
212
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149 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
196
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150 {
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151 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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152 // Allow interrupts to happen again
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153 cyg_drv_interrupt_unmask(cpd->interrupt);
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154 }
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155 #endif
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156 }
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157
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158 static int
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159 cs8900a_int_vector(struct eth_drv_sc *sc)
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160 {
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161 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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162 return (cpd->interrupt);
196
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163 }
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164
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165 static bool
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166 cs8900a_init(struct cyg_netdevtab_entry *tab)
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167 {
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168 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
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169 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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170 cyg_addrword_t base = cpd->base;
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171 cyg_uint16 chip_type, chip_rev, chip_status;
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172 cyg_uint16 i;
196
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173 long timeout = 500000;
197
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174 cyg_bool esa_configured = false;
196
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175
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176 cpd->tab = tab;
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177
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178 CYGHWR_CL_CS8900A_PLF_INIT(cpd);
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179
212
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180 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
196
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181 // Initialize environment, setup interrupt handler
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182 cyg_drv_interrupt_create(cpd->interrupt,
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183 0, // Priority - what goes here?
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184 (cyg_addrword_t)cpd, // Data item passed to interrupt handler
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185 (cyg_ISR_t *)cs8900a_isr,
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186 (cyg_DSR_t *)cs8900a_dsr,
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187 &cpd->interrupt_handle,
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188 &cpd->interrupt_object);
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189 cyg_drv_interrupt_attach(cpd->interrupt_handle);
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190 cyg_drv_interrupt_acknowledge(cpd->interrupt);
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191 cyg_drv_interrupt_unmask(cpd->interrupt);
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192
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193 #ifdef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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194 cyg_thread_create(1, // Priority
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195 cs8900a_fake_int, // entry
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196 (cyg_addrword_t)sc, // entry parameter
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197 "CS8900 int", // Name
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198 &cs8900a_fake_int_stack[0], // Stack
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199 STACK_SIZE, // Size
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200 &cs8900a_fake_int_thread_handle, // Handle
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201 &cs8900a_fake_int_thread_data // Thread data structure
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202 );
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203 cyg_thread_resume(cs8900a_fake_int_thread_handle); // Start it
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204 #endif
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205 #endif
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206
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207 // Read controller ID - the first is a dummy read, since (on some
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208 // platforms) the first access to the controller seems to skip the
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209 // MSB 8 bits.
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210 get_reg(base, PP_ChipID);
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211 chip_type = get_reg(base, PP_ChipID);
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212 chip_rev = get_reg(base, PP_ChipRev);
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213 #if DEBUG & 8
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214 diag_printf("CS8900A[%p] - type: 0x%04x, rev: 0x%04x\n", base, chip_type, chip_rev);
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215 #endif
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216 if (chip_type != PP_ChipID_CL) {
196
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217 #if DEBUG & 8
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218 diag_printf("CS8900 - invalid type (0x%04x), must be 0x630e\n", chip_type);
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219 #endif
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220 return false;
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221 }
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222
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223 CYGHWR_CL_CS8900A_PLF_RESET(base);
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224 put_reg(base, PP_SelfCtl, PP_SelfCtl_Reset); // Reset chip
208
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225
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226 CYGHWR_CL_CS8900A_PLF_POST_RESET(base);
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227
196
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228 while ((get_reg(base, PP_SelfStat) & PP_SelfStat_InitD) == 0) {
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229 if (--timeout <= 0) {
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230 #if DEBUG & 8
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231 diag_printf("CS8900 didn't reset - abort!\n");
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232 #endif
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233 return false;
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234 }
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235 }
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236
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237 chip_status = get_reg(base, PP_SelfStat);
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238 #if DEBUG & 8
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239 diag_printf("CS8900 - status: 0x%04x (%sEEPROM present)\n", chip_status,
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240 chip_status & PP_SelfStat_EEPROM ? "" : "no ");
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241 #endif
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242
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243
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244 // Disable reception whilst finding the ESA
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245 put_reg(base, PP_LineCTL, 0 );
197
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246 // Find ESA - check possible sources in sequence and stop when
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247 // one provides the ESA:
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248 // RedBoot option (via provide_esa)
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249 // Compile-time configuration
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250 // EEPROM
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251 // <fail configuration of device>
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252 if (NULL != cpd->provide_esa) {
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253 esa_configured = cpd->provide_esa(cpd);
196
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254 # if DEBUG & 8
197
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255 if (esa_configured)
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256 diag_printf("Got ESA from RedBoot option\n");
196
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257 # endif
197
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258 }
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259 if (!esa_configured && cpd->hardwired_esa) {
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260 // ESA is already set in cpd->esa[]
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261 esa_configured = true;
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262 }
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263 if (!esa_configured && (chip_status & PP_SelfStat_EEPROM)) {
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264 // Get ESA from EEPROM - via the PP_IA registers
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265 cyg_uint16 esa_word;
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266 for (i = 0; i < sizeof(cpd->esa); i += 2) {
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267 #ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
197
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268 esa_word = get_reg(base, PP_IA+i);
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269 cpd->esa[i] = (esa_word & 0xFF);
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270 cpd->esa[i+1] = (esa_word >> 8) & 0xFF;
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271 #else
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272 esa_word = get_reg(base, PP_IA+CYG_SWAP16(i));
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273 cpd->esa[i+1] = (esa_word & 0xFF);
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274 cpd->esa[i] = (esa_word >> 8) & 0xFF;
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275 #endif
196
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276 }
197
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277 esa_configured = true;
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278 }
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279 if (!esa_configured) {
196
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280 # if DEBUG & 8
197
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281 diag_printf("CS8900 - no EEPROM, static ESA or RedBoot config option.\n");
196
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282 # endif
197
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283 return false;
196
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284 }
197
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285
196
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286 // Tell the chip what ESA to use
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287 for (i = 0; i < sizeof(cpd->esa); i += 2) {
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288 #ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
196
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289 put_reg(base, PP_IA+i, cpd->esa[i] | (cpd->esa[i+1] << 8));
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290 #else
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291 put_reg(base, PP_IA+CYG_SWAP16(i), cpd->esa[i+1] | (cpd->esa[i] << 8));
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292 #endif
196
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293 }
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294 // Set logical address mask
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295 for (i = 0; i < 8; i += 2) {
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296 #ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
196
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297 put_reg(base, PP_LAF+i, 0xFFFF);
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298 #else
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299 put_reg(base, PP_LAF+CYG_SWAP16(i), 0xFFFF);
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300 #endif
196
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301 }
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302 # if DEBUG & 8
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303 diag_printf("ESA %02x:%02x:%02x:%02x:%02x:%02x\n",
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304 cpd->esa[0], cpd->esa[1], cpd->esa[2],
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305 cpd->esa[3], cpd->esa[4], cpd->esa[5]);
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306 # endif
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307
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308 // Initialize upper level driver
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309 (sc->funs->eth_drv->init)(sc, cpd->esa);
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310
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311 return true;
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312 }
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313
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314 static void
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315 cs8900a_stop(struct eth_drv_sc *sc)
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316 {
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317 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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318 cyg_addrword_t base = cpd->base;
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319
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320 put_reg(base, PP_LineCTL, 0);
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321 }
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322
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323 // This function is called to "start up" the interface. It may be called
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324 // multiple times, even when the hardware is already running. It will be
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325 // called whenever something "hardware oriented" changes and should leave
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326 // the hardware ready to send/receive packets.
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327 static void
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328 cs8900a_start(struct eth_drv_sc *sc, cyg_uint8 *esa, int flags)
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329 {
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330 cyg_uint16 stat;
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331 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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332 cyg_addrword_t base = cpd->base;
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333
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334 put_reg(base, PP_BusCtl, PP_BusCtl_MemoryE); // Disable interrupts, memory mode
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335 put_reg(base, PP_IntReg, PP_IntReg_IRQ0); // Only possibility
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336 put_reg(base, PP_RxCFG, PP_RxCFG_RxOK | PP_RxCFG_CRC |
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337 PP_RxCFG_RUNT | PP_RxCFG_EXTRA);
208
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338 cpd->rxmode = PP_RxCTL_RxOK | PP_RxCTL_Broadcast | PP_RxCTL_IA;
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339 put_reg(base, PP_RxCTL, cpd->rxmode);
196
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340 put_reg(base, PP_TxCFG, PP_TxCFG_TxOK | PP_TxCFG_Collision |
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341 PP_TxCFG_CRS | PP_TxCFG_SQE | PP_TxCFG_Late |
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342 PP_TxCFG_Jabber | PP_TxCFG_16Collisions);
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343 put_reg(base, PP_BufCFG, PP_BufCFG_TxRDY | PP_BufCFG_TxUE | PP_BufCFG_RxMiss |
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344 PP_BufCFG_TxCol | PP_BufCFG_Miss | PP_BufCFG_SWI);
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345 put_reg(base, PP_IntReg, PP_IntReg_IRQ0); // Only possibility
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346 put_reg(base, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
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347 // Clear Interrupt Status Queue before enabling interrupts
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348 do {
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349 HAL_READ_UINT16(cpd->base+CS8900A_ISQ, stat);
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350 } while (stat != 0) ;
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351 cpd->txbusy = false;
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352 put_reg(base, PP_BusCtl, PP_BusCtl_EnableIRQ);
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353 }
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354
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355 // This routine is called to perform special "control" opertions
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356 static int
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357 cs8900a_control(struct eth_drv_sc *sc, unsigned long key, void *data, int data_length)
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358 {
208
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359 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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360 cyg_addrword_t base = cpd->base;
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361 struct eth_drv_mc_list *mc_list = data;
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362
196
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363 switch (key) {
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364 case ETH_DRV_SET_MAC_ADDRESS:
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365 return 0;
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366 break;
208
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367 case ETH_DRV_SET_MC_LIST:
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368 case ETH_DRV_SET_MC_ALL:
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369 // Note: this code always accepts all multicast addresses if any
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370 // are desired. It would be possible to accept a subset by adjusting
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371 // the Logical Address Filter (LAF), but that would require scanning
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372 // this list and building a suitable mask.
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373 if (mc_list->len) {
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374 cpd->rxmode |= PP_RxCTL_Multicast;
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375 } else {
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376 cpd->rxmode &= ~PP_RxCTL_Multicast;
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377 }
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378 put_reg(base, PP_RxCTL, cpd->rxmode); // When is it safe to do this?
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379 return 0;
196
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380 default:
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381 return 1;
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382 break;
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383 }
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384 }
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385
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386 // This routine is called to see if it is possible to send another packet.
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387 // It will return non-zero if a transmit is possible, zero otherwise.
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388 static int
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389 cs8900a_can_send(struct eth_drv_sc *sc)
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390 {
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391 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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392 cyg_addrword_t base = cpd->base;
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393 cyg_uint16 stat;
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394
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395 stat = get_reg(base, PP_LineStat);
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396 if ((stat & PP_LineStat_LinkOK) == 0) {
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397 return false; // Link not connected
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398 }
212
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399 #ifdef CYGPKG_KERNEL
196
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400 // Horrible hack!
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401 if (cpd->txbusy) {
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402 cyg_tick_count_t now = cyg_current_time();
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403 if ((now - cpd->txstart) > 25) {
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404 // 250ms is more than enough to transmit one frame
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405 #if DEBUG & 1
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406 diag_printf("CS8900: Tx interrupt lost\n");
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407 #endif
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408 cpd->txbusy = false;
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409 // Free up the buffer (with error indication)
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410 (sc->funs->eth_drv->tx_done)(sc, cpd->txkey, 1);
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411 }
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412 }
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413 #endif
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414 return (cpd->txbusy == false);
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415 }
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416
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417 // This routine is called to send data to the hardware.
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418 static void
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419 cs8900a_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
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420 int total_len, unsigned long key)
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421 {
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422 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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423 cyg_addrword_t base = cpd->base;
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424 int i;
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425 int len;
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426 cyg_uint8 *data;
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427 cyg_uint16 saved_data = 0, *sdata;
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428 cyg_uint16 stat;
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429 bool odd_byte = false;
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430
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431 // Mark xmitter busy
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432 cpd->txbusy = true;
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433 cpd->txkey = key;
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434 #ifdef CYGPKG_KERNEL
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435 cpd->txstart = cyg_current_time();
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436 #endif
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437
196
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438 // Start the xmit sequence
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439 #ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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440 total_len = CYG_SWAP16(total_len);
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441 #endif
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442
196
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443 // The hardware indicates that there are options as to when the actual
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444 // packet transmission will start wrt moving of data into the transmit
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445 // buffer. However, impirical results seem to indicate that if the
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446 // packet is large and transmission is allowed to start before the
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447 // entire packet has been pushed into the buffer, the hardware gets
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448 // confused and the packet is lost, along with a "lost" Tx interrupt.
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449 // This may be a case of the copy loop below being interrupted, e.g.
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450 // a system timer interrupt, and the hardware getting unhappy that
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451 // not all of the data was provided before the transmission should
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452 // have completed (i.e. buffer underrun).
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453 // For now, the solution is to not allow this overlap.
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454 //HAL_WRITE_UINT16(cpd->base+CS8900A_TxCMD, PP_TxCmd_TxStart_5)
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455
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456 // Start only when all data sent to chip
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457 HAL_WRITE_UINT16(cpd->base+CS8900A_TxCMD, PP_TxCmd_TxStart_Full);
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458
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459 HAL_WRITE_UINT16(cpd->base+CS8900A_TxLEN, total_len);
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460 // Wait for controller ready signal
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461 do {
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462 stat = get_reg(base, PP_BusStat);
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463 } while (!(stat & PP_BusStat_TxRDY));
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464
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465 // Put data into buffer
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466 for (i = 0; i < sg_len; i++) {
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467 data = (cyg_uint8 *)sg_list[i].buf;
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468 len = sg_list[i].len;
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469
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470 if (len > 0) {
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471 /* Finish the last word. */
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472 if (odd_byte) {
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473 // This new byte must get on the bus _after_ the last saved odd byte, it therefore
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474 // belongs in the MSB of the CS8900a
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475 #ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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476 saved_data |= *data++;
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477 #else
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478 saved_data |= ((cyg_uint16)*data++) << 8;
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479 #endif
196
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480 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
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481 len--;
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482 odd_byte = false;
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483 }
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484 if (((CYG_ADDRESS)data & 0x1) == 0) {
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485 /* Aligned on 16-bit boundary, so output contiguous words. */
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486 sdata = (cyg_uint16 *)data;
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487 while (len > 1) {
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488 // Make sure data get on the bus in Big Endian format
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489 #if((CYG_BYTEORDER == CYG_MSBFIRST) && defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED) || \
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490 (CYG_BYTEORDER == CYG_LSBFIRST) && !defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED ))
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491 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, *sdata++);
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492 #else
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493 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, CYG_SWAP16(*sdata++));
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494 #endif
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495 len -= sizeof(cyg_uint16);
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496 }
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497 data = (cyg_uint8 *)sdata;
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498 } else {
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499 /* Not 16-bit aligned, so byte copy */
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500 while (len > 1) {
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501 saved_data = (cyg_uint16)*data++; // reuse saved_data
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502 // Make sure data get on the bus in Big Endian format, the first byte belongs in the
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503 // LSB of the CS8900A
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504 #ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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505 saved_data = ((cyg_uint16)*data++) | (saved_data << 8);
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506 #else
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507 saved_data |= ((cyg_uint16)*data++) << 8;
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508 #endif
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509 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
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510 len -= sizeof(cyg_uint16);
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511 }
196
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512 }
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513 /* Save last byte, if necessary. */
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514 if (len == 1) {
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515 saved_data = (cyg_uint16)*data;
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516 // This _last_ byte must get on the bus _first_, it therefore belongs in the LSB of
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517 // the CS8900a
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518 #ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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519 saved_data = (saved_data << 8);
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520 #endif
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521 odd_byte = true;
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522 }
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523 }
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524 }
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525 if (odd_byte) {
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526 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
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527 }
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528 }
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529
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530 // This function is called when a packet has been received. It's job is
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531 // to prepare to unload the packet from the hardware. Once the length of
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532 // the packet is known, the upper layer of the driver can be told. When
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533 // the upper layer is ready to unload the packet, the internal function
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534 // 'cs8900a_recv' will be called to actually fetch it from the hardware.
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535 static void
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536 cs8900a_RxEvent(struct eth_drv_sc *sc, int stat)
196
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537 {
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538 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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parents:
diff changeset
539 cyg_addrword_t base = cpd->base;
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jlarmour
parents: 1599
diff changeset
540 cyg_uint16 len;
196
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diff changeset
541
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parents: 1599
diff changeset
542 if(stat & PP_RxCFG_RxOK) {
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jlarmour
parents: 1599
diff changeset
543 // Only start reading a message if one has been received
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diff changeset
544 HAL_READ_UINT16(base+CS8900A_RTDATA, stat);
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diff changeset
545 HAL_READ_UINT16(base+CS8900A_RTDATA, len);
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diff changeset
546
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diff changeset
547 #ifdef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
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diff changeset
548 len = CYG_SWAP16(len);
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diff changeset
549 #endif
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diff changeset
550
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parents: 1599
diff changeset
551 CYG_ASSERT(len > 0, "Zero length ethernet frame received");
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diff changeset
552
196
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553 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
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parents: 1599
diff changeset
554 if (cyg_io_eth_net_debug) {
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parents: 1599
diff changeset
555 diag_printf("RxEvent - stat: %x, len: %d\n", stat, len);
e2264d5f9337 * src/if_cs8900a.c: Drop "ghost" frames with zero length
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diff changeset
556 }
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parents: 1599
diff changeset
557 #endif
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jlarmour
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diff changeset
558 (sc->funs->eth_drv->recv)(sc, len);
196
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559 }
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diff changeset
560 }
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diff changeset
561
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jlarmour
parents:
diff changeset
562 // This function is called as a result of the "eth_drv_recv()" call above.
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563 // It's job is to actually fetch data for a packet from the hardware once
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jlarmour
parents:
diff changeset
564 // memory buffers have been allocated for the packet. Note that the buffers
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
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parents:
diff changeset
565 // may come in pieces, using a scatter-gather list. This allows for more
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
jlarmour
parents:
diff changeset
566 // efficient processing in the upper layers of the stack.
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diff changeset
567 static void
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parents:
diff changeset
568 cs8900a_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
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parents:
diff changeset
569 {
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diff changeset
570 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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diff changeset
571 cyg_addrword_t base = cpd->base;
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parents:
diff changeset
572 int i, mlen;
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parents:
diff changeset
573 cyg_uint16 *data, val;
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parents:
diff changeset
574 cyg_uint8 *cp, cval;
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parents:
diff changeset
575
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parents:
diff changeset
576 for (i = 0; i < sg_len; i++) {
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jlarmour
parents:
diff changeset
577 data = (cyg_uint16 *)sg_list[i].buf;
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jlarmour
parents:
diff changeset
578 mlen = sg_list[i].len;
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jlarmour
parents:
diff changeset
579 while (mlen >= sizeof(*data)) {
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parents:
diff changeset
580 HAL_READ_UINT16(base+CS8900A_RTDATA, val);
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jlarmour
parents:
diff changeset
581 if (data) {
1599
bf994e1a516c Big/Little endian changes from Bob Koninckx
gthomas
parents: 1397
diff changeset
582 #if((CYG_BYTEORDER == CYG_MSBFIRST) && defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED) || \
bf994e1a516c Big/Little endian changes from Bob Koninckx
gthomas
parents: 1397
diff changeset
583 (CYG_BYTEORDER == CYG_LSBFIRST) && !defined(CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED ))
196
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diff changeset
584 *data++ = val;
1599
bf994e1a516c Big/Little endian changes from Bob Koninckx
gthomas
parents: 1397
diff changeset
585 #else
bf994e1a516c Big/Little endian changes from Bob Koninckx
gthomas
parents: 1397
diff changeset
586 *data++ = CYG_SWAP16(val);
bf994e1a516c Big/Little endian changes from Bob Koninckx
gthomas
parents: 1397
diff changeset
587 #endif
196
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parents:
diff changeset
588 }
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jlarmour
parents:
diff changeset
589 mlen -= sizeof(*data);
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parents:
diff changeset
590 }
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jlarmour
parents:
diff changeset
591 if (mlen) {
941
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parents: 219
diff changeset
592 HAL_READ_UINT16(base+CS8900A_RTDATA, val);
1599
bf994e1a516c Big/Little endian changes from Bob Koninckx
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parents: 1397
diff changeset
593 #ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
941
01d8c3c977d9 * src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
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parents: 219
diff changeset
594 // last odd byte will be in the LSB
01d8c3c977d9 * src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
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parents: 219
diff changeset
595 cval = (cyg_uint8)(val);
01d8c3c977d9 * src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
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parents: 219
diff changeset
596 #elif(CYG_BYTEORDER == CYG_MSBFIRST)
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parents: 219
diff changeset
597 // last odd byte will be in the MSB
01d8c3c977d9 * src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
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diff changeset
598 cval = (cyg_uint8)(val >> 8);
01d8c3c977d9 * src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
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diff changeset
599 #endif
01d8c3c977d9 * src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
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parents: 219
diff changeset
600 cval &= 0xff;
196
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
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parents:
diff changeset
601 if ((cp = (cyg_uint8 *)data) != 0) {
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
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parents:
diff changeset
602 *cp = cval;
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
jlarmour
parents:
diff changeset
603 }
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jlarmour
parents:
diff changeset
604 }
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jlarmour
parents:
diff changeset
605 }
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jlarmour
parents:
diff changeset
606 }
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jlarmour
parents:
diff changeset
607
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jlarmour
parents:
diff changeset
608 static void
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parents:
diff changeset
609 cs8900a_TxEvent(struct eth_drv_sc *sc, int stat)
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parents:
diff changeset
610 {
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
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parents:
diff changeset
611 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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jlarmour
parents:
diff changeset
612 cyg_addrword_t base = cpd->base;
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diff changeset
613
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jlarmour
parents:
diff changeset
614 stat = get_reg(base, PP_TER);
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jlarmour
parents:
diff changeset
615 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
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parents:
diff changeset
616 if (cyg_io_eth_net_debug) {
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diff changeset
617 diag_printf("Tx event: %x\n", stat);
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618 }
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diff changeset
619 #endif
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diff changeset
620 cpd->txbusy = false;
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jlarmour
parents:
diff changeset
621 (sc->funs->eth_drv->tx_done)(sc, cpd->txkey, 0);
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diff changeset
622 }
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jlarmour
parents:
diff changeset
623
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jlarmour
parents:
diff changeset
624 static void
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diff changeset
625 cs8900a_BufEvent(struct eth_drv_sc *sc, int stat)
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diff changeset
626 {
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parents:
diff changeset
627 if (stat & PP_BufCFG_RxMiss) {
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parents:
diff changeset
628 }
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
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parents:
diff changeset
629 if (stat & PP_BufCFG_TxUE) {
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parents:
diff changeset
630 }
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
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parents:
diff changeset
631 }
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parents:
diff changeset
632
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parents:
diff changeset
633 static void
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jlarmour
parents:
diff changeset
634 cs8900a_poll(struct eth_drv_sc *sc)
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jlarmour
parents:
diff changeset
635 {
9b55e9c69693 Merge from eCos master repository on 2001-11-23-15:32:03-GMT
jlarmour
parents:
diff changeset
636 cyg_uint16 event;
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parents:
diff changeset
637 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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diff changeset
638 cyg_addrword_t base = cpd->base;
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parents:
diff changeset
639
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diff changeset
640 HAL_READ_UINT16(base+CS8900A_ISQ, event);
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jlarmour
parents:
diff changeset
641 while (event != 0) {
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jlarmour
parents:
diff changeset
642 switch (event & ISQ_EventMask) {
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parents:
diff changeset
643 case ISQ_RxEvent:
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parents: 1599
diff changeset
644 cs8900a_RxEvent(sc, event);
196
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parents:
diff changeset
645 break;
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parents:
diff changeset
646 case ISQ_TxEvent:
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parents:
diff changeset
647 cs8900a_TxEvent(sc, event);
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diff changeset
648 break;
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parents:
diff changeset
649 case ISQ_BufEvent:
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parents:
diff changeset
650 cs8900a_BufEvent(sc, event);
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parents:
diff changeset
651 break;
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parents:
diff changeset
652 case ISQ_RxMissEvent:
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jlarmour
parents:
diff changeset
653 // Receive miss counter has overflowed
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parents:
diff changeset
654 break;
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diff changeset
655 case ISQ_TxColEvent:
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parents:
diff changeset
656 // Transmit collision counter has overflowed
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diff changeset
657 break;
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parents:
diff changeset
658 default:
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parents:
diff changeset
659 #if DEBUG & 1
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parents:
diff changeset
660 diag_printf("%s: Unknown event: %x\n", __FUNCTION__, event);
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parents:
diff changeset
661 #endif
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parents:
diff changeset
662 break;
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parents:
diff changeset
663 }
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diff changeset
664 HAL_READ_UINT16(base+CS8900A_ISQ, event);
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parents:
diff changeset
665 }
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diff changeset
666
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diff changeset
667 CYGHWR_CL_CS8900A_PLF_INT_CLEAR(cpd);
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parents:
diff changeset
668 }
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parents:
diff changeset
669
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diff changeset
670 #ifdef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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parents:
diff changeset
671 void
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diff changeset
672 cs8900a_fake_int(cyg_addrword_t param)
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diff changeset
673 {
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diff changeset
674 struct eth_drv_sc *sc = (struct eth_drv_sc *) param;
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675 int s;
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676
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677 #if DEBUG & 1
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678 diag_printf("cs8900a_fake_int()\n");
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679 #endif
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680
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681 while (true) {
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682 cyg_thread_delay(5);
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683 s = splnet();
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684 cs8900a_poll(sc);
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685 splx(s);
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686 }
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687 }
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688 #endif