Mercurial > flash_v2
annotate packages/hal/arm/aeb/current/include/hal_cache.h @ 1777:c16341b1bac6 default tip
* Added execute permissions to files missed in conversion from CVS
| author | alexs |
|---|---|
| date | Mon, 12 Oct 2009 02:26:09 +0100 |
| parents | d2c90368aeef |
| children |
| rev | line source |
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| 2 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
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11 //####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License along |
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26 // with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use macros |
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30 // or inline functions from this file, or you compile this file and link it |
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31 // with other works to produce a work based on this file, this file does not |
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32 // by itself cause the resulting work to be covered by the GNU General Public |
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33 // License. However the source code for this file must still be made available |
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34 // in accordance with section (3) of the GNU General Public License. |
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35 // |
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36 // This exception does not invalidate any other reasons why a work based on |
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37 // this file might be covered by the GNU General Public License. |
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38 // |
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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40 // at http://sources.redhat.com/ecos/ecos-license/ |
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41 // ------------------------------------------- |
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42 //####ECOSGPLCOPYRIGHTEND#### |
| 2 | 43 //============================================================================= |
| 44 //#####DESCRIPTIONBEGIN#### | |
| 45 // | |
| 46 // Author(s): nickg, gthomas | |
| 47 // Contributors: nickg, gthomas | |
| 48 // Date: 1998-09-28 | |
| 49 // Purpose: Cache control API | |
| 50 // Description: The macros defined here provide the HAL APIs for handling | |
| 51 // cache control operations. | |
| 52 // Usage: | |
| 53 // #include <cyg/hal/hal_cache.h> | |
| 54 // ... | |
| 55 // | |
| 56 // | |
| 57 //####DESCRIPTIONEND#### | |
| 58 // | |
| 59 //============================================================================= | |
| 60 | |
| 61 #include <cyg/infra/cyg_type.h> | |
| 62 #include <cyg/hal/hal_io.h> | |
| 63 | |
| 64 //----------------------------------------------------------------------------- | |
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65 // Cache dimensions - one unified cache |
| 2 | 66 |
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67 #define HAL_CACHE_UNIFIED |
| 2 | 68 |
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69 #define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes |
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70 #define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line |
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71 #define HAL_UCACHE_WAYS 4 // Associativity of the cache |
| 2 | 72 |
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73 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) |
| 2 | 74 |
| 75 // Cache & SRAM control | |
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76 #define CYG_DEVICE_CCR 0xFFFFA400 |
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77 #define CYG_DEVICE_LSCR 0xFFFFA404 |
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78 #define CYG_DEVICE_CACHE_MEM 0x60000800 |
| 2 | 79 |
| 80 #define CCR_E 0x01 // Cache enabled | |
| 81 #define CCR_S 0x02 // SRAM mode enabled | |
| 82 #define CCR_F 0x04 // Flush mode enabled | |
| 83 #define CCR_I 0x08 // Invalidate mode | |
| 84 | |
| 85 #define LCSR_E 0x01 // Local SRAM enabled | |
| 86 #define LCSR_L 0x02 // Local SRAM mapped to high memory | |
| 87 | |
| 88 //----------------------------------------------------------------------------- | |
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89 // Global control of cache |
| 2 | 90 |
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91 // Enable the cache |
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92 #define HAL_UCACHE_ENABLE() \ |
| 2 | 93 { \ |
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94 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \ |
| 2 | 95 } |
| 96 | |
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97 // Disable the cache |
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98 #define HAL_UCACHE_DISABLE() \ |
| 2 | 99 { \ |
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100 HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \ |
| 2 | 101 } |
| 102 | |
| 103 // Invalidate the entire cache | |
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104 #define HAL_UCACHE_INVALIDATE_ALL() \ |
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105 { \ |
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106 register cyg_uint8 old_ccr; \ |
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107 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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108 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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109 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
| 2 | 110 } |
| 111 | |
| 112 // Synchronize the contents of the cache with memory. | |
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113 #define HAL_UCACHE_SYNC() \ |
| 2 | 114 { \ |
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115 register volatile cyg_uint32 *cache_SRAM = \ |
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116 (volatile cyg_uint32*) CYG_DEVICE_CACHE_MEM; \ |
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117 register int i; \ |
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118 register cyg_uint8 old_ccr; \ |
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119 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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120 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \ |
| 2 | 121 for (i = 0; i < HAL_DCACHE_SETS; i++) { \ |
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122 cyg_uint32 tmp = *cache_SRAM++; \ |
| 2 | 123 } \ |
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124 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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125 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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126 } |
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127 |
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128 // Query the state of the cache |
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129 #define HAL_UCACHE_IS_ENABLED(_state_) \ |
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130 { \ |
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131 cyg_uint8 __ccr; \ |
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132 HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \ |
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133 (_state_) = (CCR_E == __ccr) ? 1 : 0; \ |
| 2 | 134 } |
| 135 | |
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136 // Purge contents of cache |
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137 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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138 |
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139 // Set the cache refill burst size |
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140 //#define HAL_UCACHE_BURST_SIZE(_size_) |
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141 |
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142 // Set the cache write mode |
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143 //#define HAL_UCACHE_WRITE_MODE( _mode_ ) |
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144 |
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145 //#define HAL_UCACHE_WRITETHRU_MODE 0 |
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146 //#define HAL_UCACHE_WRITEBACK_MODE 1 |
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147 |
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148 // Load the contents of the given address range into the cache |
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149 // and then lock the cache so that it stays there. |
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150 //#define HAL_UCACHE_LOCK(_base_, _size_) |
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151 |
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152 // Undo a previous lock operation |
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153 //#define HAL_UCACHE_UNLOCK(_base_, _size_) |
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154 |
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155 // Unlock entire cache |
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156 //#define HAL_UCACHE_UNLOCK_ALL() |
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157 |
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158 //----------------------------------------------------------------------------- |
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159 // Cache line control |
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160 |
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161 // Allocate cache lines for the given address range without reading its |
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162 // contents from memory. |
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163 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) |
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164 |
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165 // Write dirty cache lines to memory and invalidate the cache entries |
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166 // for the given address range. |
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167 //#define HAL_UCACHE_FLUSH( _base_ , _size_ ) |
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168 |
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169 // Invalidate cache lines in the given range without writing to memory. |
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170 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) |
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171 |
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172 // Write dirty cache lines to memory for the given address range. |
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173 //#define HAL_UCACHE_STORE( _base_ , _size_ ) |
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174 |
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175 // Preread the given range into the cache with the intention of reading |
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176 // from it later. |
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177 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) |
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178 |
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179 // Preread the given range into the cache with the intention of writing |
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180 // to it later. |
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181 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) |
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182 |
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183 // Allocate and zero the cache lines associated with the given range. |
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184 //#define HAL_UCACHE_ZERO( _base_ , _size_ ) |
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185 |
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186 //----------------------------------------------------------------------------- |
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187 |
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188 //----------------------------------------------------------------------------- |
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189 // Data and instruction cache macros map onto the both-cache macros |
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190 |
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191 //----------------------------------------------------------------------------- |
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192 // Global control of data cache |
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193 |
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194 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE |
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195 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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196 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS |
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197 #define HAL_DCACHE_SETS HAL_UCACHE_SETS |
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198 |
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199 // Enable the data cache |
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200 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() |
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201 |
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202 // Disable the data cache |
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203 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() |
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204 |
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205 // Invalidate the entire cache |
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206 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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207 |
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208 // Synchronize the contents of the cache with memory. |
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209 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() |
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210 |
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211 // Query the state of the data cache |
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212 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 213 |
| 214 // Set the data cache refill burst size | |
| 215 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 216 | |
| 217 // Set the data cache write mode | |
| 218 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 219 | |
| 220 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 221 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 222 | |
| 223 // Load the contents of the given address range into the data cache | |
| 224 // and then lock the cache so that it stays there. | |
| 225 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 226 | |
| 227 // Undo a previous lock operation | |
| 228 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 229 | |
| 230 // Unlock entire cache | |
| 231 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 232 | |
| 233 //----------------------------------------------------------------------------- | |
| 234 // Data cache line control | |
| 235 | |
| 236 // Allocate cache lines for the given address range without reading its | |
| 237 // contents from memory. | |
| 238 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 239 | |
| 240 // Write dirty cache lines to memory and invalidate the cache entries | |
| 241 // for the given address range. | |
| 242 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 243 | |
| 244 // Invalidate cache lines in the given range without writing to memory. | |
| 245 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 246 | |
| 247 // Write dirty cache lines to memory for the given address range. | |
| 248 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 249 | |
| 250 // Preread the given range into the cache with the intention of reading | |
| 251 // from it later. | |
| 252 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 253 | |
| 254 // Preread the given range into the cache with the intention of writing | |
| 255 // to it later. | |
| 256 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 257 | |
| 258 // Allocate and zero the cache lines associated with the given range. | |
| 259 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 260 | |
| 261 //----------------------------------------------------------------------------- | |
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262 // Global control of Instruction cache |
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263 |
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264 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE |
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265 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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266 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS |
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267 #define HAL_ICACHE_SETS HAL_UCACHE_SETS |
| 2 | 268 |
| 269 // Enable the instruction cache | |
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270 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() |
| 2 | 271 |
| 272 // Disable the instruction cache | |
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273 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() |
| 2 | 274 |
| 275 // Invalidate the entire cache | |
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276 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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277 |
| 2 | 278 |
| 279 // Synchronize the contents of the cache with memory. | |
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280 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() |
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281 |
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282 // Query the state of the instruction cache |
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283 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 284 |
| 285 // Set the instruction cache refill burst size | |
| 286 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 287 | |
| 288 // Load the contents of the given address range into the instruction cache | |
| 289 // and then lock the cache so that it stays there. | |
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290 |
| 2 | 291 //#define HAL_ICACHE_LOCK(_base_, _size_) |
| 292 | |
| 293 // Undo a previous lock operation | |
| 294 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 295 | |
| 296 // Unlock entire cache | |
| 297 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 298 | |
| 299 //----------------------------------------------------------------------------- | |
| 300 // Instruction cache line control | |
| 301 | |
| 302 // Invalidate cache lines in the given range without writing to memory. | |
| 303 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 304 | |
| 305 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 306 // End of hal_cache.h |
