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1 #ifndef CYGONCE_HAL_CACHE_H |
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2 #define CYGONCE_HAL_CACHE_H |
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3 |
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4 //============================================================================= |
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5 // |
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6 // hal_cache.h |
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7 // |
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8 // HAL cache control API |
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9 // |
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10 //============================================================================= |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //============================================================================= |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg, gthomas |
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36 // Contributors: nickg, gthomas |
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37 // Date: 1998-09-28 |
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38 // Purpose: Cache control API |
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39 // Description: The macros defined here provide the HAL APIs for handling |
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40 // cache control operations. |
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41 // Usage: |
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42 // #include <cyg/hal/hal_cache.h> |
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43 // ... |
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44 // |
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45 // |
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46 //####DESCRIPTIONEND#### |
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47 // |
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48 //============================================================================= |
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49 |
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50 #include <cyg/infra/cyg_type.h> |
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51 #include <cyg/hal/hal_io.h> |
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52 |
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53 //----------------------------------------------------------------------------- |
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54 // Cache dimensions |
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55 |
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56 // Data cache |
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57 #define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes |
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58 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line |
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59 #define HAL_DCACHE_WAYS 4 // Associativity of the cache |
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60 |
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61 // Instruction cache |
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62 #define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes |
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63 #define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line |
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64 #define HAL_ICACHE_WAYS 4 // Associativity of the cache |
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65 |
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66 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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67 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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68 |
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69 // Cache & SRAM control |
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70 #define CYG_DEVICE_CCR ((volatile cyg_uint8 *)0xFFFFA400) |
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71 #define CYG_DEVICE_LSCR ((volatile cyg_uint8 *)0xFFFFA404) |
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72 |
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73 #define CCR_E 0x01 // Cache enabled |
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74 #define CCR_S 0x02 // SRAM mode enabled |
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75 #define CCR_F 0x04 // Flush mode enabled |
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76 #define CCR_I 0x08 // Invalidate mode |
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77 |
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78 #define LCSR_E 0x01 // Local SRAM enabled |
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79 #define LCSR_L 0x02 // Local SRAM mapped to high memory |
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80 |
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81 //----------------------------------------------------------------------------- |
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82 // Global control of data cache |
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83 |
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84 // Enable the data cache |
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85 #define HAL_DCACHE_ENABLE() \ |
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86 { \ |
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87 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_E); \ |
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88 } |
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89 |
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90 // Disable the data cache |
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91 #define HAL_DCACHE_DISABLE() \ |
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92 { \ |
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93 HAL_WRITE_UINT32(CYG_DEVICE_CCR, 0); \ |
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94 } |
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95 |
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96 // Invalidate the entire cache |
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97 #define HAL_DCACHE_INVALIDATE_ALL() \ |
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98 { \ |
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99 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \ |
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100 } |
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101 |
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102 // Synchronize the contents of the cache with memory. |
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103 #define HAL_DCACHE_SYNC() \ |
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104 { \ |
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105 cyg_uint32 *cache_SRAM = (cyg_uint32 *)0x60000800; \ |
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106 int i; \ |
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107 cyg_uint32 old_ccr; \ |
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108 HAL_READ_UINT32(CYG_DEVICE_CCR, old_ccr); \ |
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109 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_F); \ |
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110 for (i = 0; i < HAL_DCACHE_SETS; i++) { \ |
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111 *cache_SRAM = 0; \ |
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112 cache_SRAM += HAL_DCACHE_LINE_SIZE; \ |
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113 } \ |
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114 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \ |
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115 HAL_WRITE_UINT32(CYG_DEVICE_CCR, old_ccr); \ |
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116 } |
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117 |
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118 // Purge contents of data cache |
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119 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_INVALIDATE_ALL() |
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120 |
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121 // Set the data cache refill burst size |
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122 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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123 |
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124 // Set the data cache write mode |
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125 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
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126 |
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127 //#define HAL_DCACHE_WRITETHRU_MODE 0 |
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128 //#define HAL_DCACHE_WRITEBACK_MODE 1 |
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129 |
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130 // Load the contents of the given address range into the data cache |
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131 // and then lock the cache so that it stays there. |
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132 //#define HAL_DCACHE_LOCK(_base_, _size_) |
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133 |
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134 // Undo a previous lock operation |
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135 //#define HAL_DCACHE_UNLOCK(_base_, _size_) |
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136 |
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137 // Unlock entire cache |
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138 //#define HAL_DCACHE_UNLOCK_ALL() |
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139 |
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140 //----------------------------------------------------------------------------- |
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141 // Data cache line control |
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142 |
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143 // Allocate cache lines for the given address range without reading its |
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144 // contents from memory. |
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145 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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146 |
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147 // Write dirty cache lines to memory and invalidate the cache entries |
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148 // for the given address range. |
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149 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
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150 |
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151 // Invalidate cache lines in the given range without writing to memory. |
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152 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
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153 |
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154 // Write dirty cache lines to memory for the given address range. |
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155 //#define HAL_DCACHE_STORE( _base_ , _size_ ) |
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156 |
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157 // Preread the given range into the cache with the intention of reading |
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158 // from it later. |
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159 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
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160 |
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161 // Preread the given range into the cache with the intention of writing |
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162 // to it later. |
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163 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
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164 |
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165 // Allocate and zero the cache lines associated with the given range. |
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166 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
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167 |
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168 //----------------------------------------------------------------------------- |
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169 // Global control of Instruction cache - use Data cache controls since they |
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170 // are not separatable. |
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171 |
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172 // Enable the instruction cache |
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173 #define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() |
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174 |
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175 // Disable the instruction cache |
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176 #define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() |
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177 |
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178 // Invalidate the entire cache |
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179 #define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL() |
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180 |
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181 // Synchronize the contents of the cache with memory. |
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182 #define HAL_ICACHE_SYNC() |
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183 |
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184 // Set the instruction cache refill burst size |
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185 //#define HAL_ICACHE_BURST_SIZE(_size_) |
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186 |
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187 // Load the contents of the given address range into the instruction cache |
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188 // and then lock the cache so that it stays there. |
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189 //#define HAL_ICACHE_LOCK(_base_, _size_) |
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190 |
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191 // Undo a previous lock operation |
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192 //#define HAL_ICACHE_UNLOCK(_base_, _size_) |
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193 |
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194 // Unlock entire cache |
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195 //#define HAL_ICACHE_UNLOCK_ALL() |
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196 |
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197 //----------------------------------------------------------------------------- |
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198 // Instruction cache line control |
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199 |
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200 // Invalidate cache lines in the given range without writing to memory. |
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201 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
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202 |
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203 //----------------------------------------------------------------------------- |
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204 #endif // ifndef CYGONCE_HAL_CACHE_H |
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205 // End of hal_cache.h |
