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comparison packages/hal/arm/aeb/current/include/hal_cache.h @ 2:443894e2e912 ecos-v1_2_1-release

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Block commit of eCos version 1.2.1
author jlarmour
date Tue, 11 May 1999 12:24:34 +0000
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1:72f549f0d891 2:443894e2e912
1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
3
4 //=============================================================================
5 //
6 // hal_cache.h
7 //
8 // HAL cache control API
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): nickg, gthomas
36 // Contributors: nickg, gthomas
37 // Date: 1998-09-28
38 // Purpose: Cache control API
39 // Description: The macros defined here provide the HAL APIs for handling
40 // cache control operations.
41 // Usage:
42 // #include <cyg/hal/hal_cache.h>
43 // ...
44 //
45 //
46 //####DESCRIPTIONEND####
47 //
48 //=============================================================================
49
50 #include <cyg/infra/cyg_type.h>
51 #include <cyg/hal/hal_io.h>
52
53 //-----------------------------------------------------------------------------
54 // Cache dimensions
55
56 // Data cache
57 #define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes
58 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
59 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
60
61 // Instruction cache
62 #define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes
63 #define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line
64 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
65
66 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
67 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
68
69 // Cache & SRAM control
70 #define CYG_DEVICE_CCR ((volatile cyg_uint8 *)0xFFFFA400)
71 #define CYG_DEVICE_LSCR ((volatile cyg_uint8 *)0xFFFFA404)
72
73 #define CCR_E 0x01 // Cache enabled
74 #define CCR_S 0x02 // SRAM mode enabled
75 #define CCR_F 0x04 // Flush mode enabled
76 #define CCR_I 0x08 // Invalidate mode
77
78 #define LCSR_E 0x01 // Local SRAM enabled
79 #define LCSR_L 0x02 // Local SRAM mapped to high memory
80
81 //-----------------------------------------------------------------------------
82 // Global control of data cache
83
84 // Enable the data cache
85 #define HAL_DCACHE_ENABLE() \
86 { \
87 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_E); \
88 }
89
90 // Disable the data cache
91 #define HAL_DCACHE_DISABLE() \
92 { \
93 HAL_WRITE_UINT32(CYG_DEVICE_CCR, 0); \
94 }
95
96 // Invalidate the entire cache
97 #define HAL_DCACHE_INVALIDATE_ALL() \
98 { \
99 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \
100 }
101
102 // Synchronize the contents of the cache with memory.
103 #define HAL_DCACHE_SYNC() \
104 { \
105 cyg_uint32 *cache_SRAM = (cyg_uint32 *)0x60000800; \
106 int i; \
107 cyg_uint32 old_ccr; \
108 HAL_READ_UINT32(CYG_DEVICE_CCR, old_ccr); \
109 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_F); \
110 for (i = 0; i < HAL_DCACHE_SETS; i++) { \
111 *cache_SRAM = 0; \
112 cache_SRAM += HAL_DCACHE_LINE_SIZE; \
113 } \
114 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \
115 HAL_WRITE_UINT32(CYG_DEVICE_CCR, old_ccr); \
116 }
117
118 // Purge contents of data cache
119 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_INVALIDATE_ALL()
120
121 // Set the data cache refill burst size
122 //#define HAL_DCACHE_BURST_SIZE(_size_)
123
124 // Set the data cache write mode
125 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
126
127 //#define HAL_DCACHE_WRITETHRU_MODE 0
128 //#define HAL_DCACHE_WRITEBACK_MODE 1
129
130 // Load the contents of the given address range into the data cache
131 // and then lock the cache so that it stays there.
132 //#define HAL_DCACHE_LOCK(_base_, _size_)
133
134 // Undo a previous lock operation
135 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
136
137 // Unlock entire cache
138 //#define HAL_DCACHE_UNLOCK_ALL()
139
140 //-----------------------------------------------------------------------------
141 // Data cache line control
142
143 // Allocate cache lines for the given address range without reading its
144 // contents from memory.
145 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
146
147 // Write dirty cache lines to memory and invalidate the cache entries
148 // for the given address range.
149 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
150
151 // Invalidate cache lines in the given range without writing to memory.
152 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
153
154 // Write dirty cache lines to memory for the given address range.
155 //#define HAL_DCACHE_STORE( _base_ , _size_ )
156
157 // Preread the given range into the cache with the intention of reading
158 // from it later.
159 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
160
161 // Preread the given range into the cache with the intention of writing
162 // to it later.
163 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
164
165 // Allocate and zero the cache lines associated with the given range.
166 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
167
168 //-----------------------------------------------------------------------------
169 // Global control of Instruction cache - use Data cache controls since they
170 // are not separatable.
171
172 // Enable the instruction cache
173 #define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
174
175 // Disable the instruction cache
176 #define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
177
178 // Invalidate the entire cache
179 #define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL()
180
181 // Synchronize the contents of the cache with memory.
182 #define HAL_ICACHE_SYNC()
183
184 // Set the instruction cache refill burst size
185 //#define HAL_ICACHE_BURST_SIZE(_size_)
186
187 // Load the contents of the given address range into the instruction cache
188 // and then lock the cache so that it stays there.
189 //#define HAL_ICACHE_LOCK(_base_, _size_)
190
191 // Undo a previous lock operation
192 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
193
194 // Unlock entire cache
195 //#define HAL_ICACHE_UNLOCK_ALL()
196
197 //-----------------------------------------------------------------------------
198 // Instruction cache line control
199
200 // Invalidate cache lines in the given range without writing to memory.
201 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
202
203 //-----------------------------------------------------------------------------
204 #endif // ifndef CYGONCE_HAL_CACHE_H
205 // End of hal_cache.h