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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 // Copyright (C) 2002, 2003 Gary Thomas
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors:nickg, jskov
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48 // Date: 2000-04-02
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49 // Purpose: Variant cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations on the PPC60x variant CPUs.
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52 // Usage: Is included via the architecture cache header:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61 #include <cyg/infra/cyg_type.h>
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62
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63 #include <cyg/hal/ppc_regs.h>
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64
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65 #include <cyg/hal/plf_cache.h>
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66
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67
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68 //-----------------------------------------------------------------------------
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69 // Cache dimensions
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70
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71 #if defined(CYGHWR_HAL_POWERPC_PPC4XX_403)
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72 // Data cache
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73 #define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
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74 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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75 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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76
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77 // Instruction cache
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78 #define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
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79 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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80 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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81 #endif // 403
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82
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83 #if defined(CYGHWR_HAL_POWERPC_PPC4XX_405) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP)
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84 // Data cache
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85 #define HAL_DCACHE_SIZE (16*1024) // Size of data cache in bytes
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86 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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87 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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88
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89 // Instruction cache
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90 #define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
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91 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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92 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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93 #endif // 405
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94
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95 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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96 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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97
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98 //-----------------------------------------------------------------------------
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99 // Global control of data cache
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100
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101 // Enable the data cache - this is implicit whenever the MMU is turned on
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102 #define HAL_DCACHE_ENABLE()
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103
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104 // Disable the data cache
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105 #define HAL_DCACHE_DISABLE()
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106
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107 // Invalidate the entire cache
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108 #define HAL_DCACHE_INVALIDATE_ALL() \
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109 CYG_MACRO_START \
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110 int _i_, _ix_, _indx_; \
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111 _indx_ = 0; \
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112 _ix_ = HAL_DCACHE_SIZE/2; \
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113 for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \
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114 asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \
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115 asm volatile ("dccci %1,%0;" :: "r"(_indx_), "r"(_ix_)); \
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116 _indx_ += HAL_DCACHE_LINE_SIZE; \
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117 } \
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118 CYG_MACRO_END
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119
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120 #if 0
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121 // Synchronize the contents of the cache with memory.
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122 #define HAL_DCACHE_SYNC() \
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123 CYG_MACRO_START \
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124 int _indx_; \
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125 for (_indx_ = 0; _indx_ < HAL_DCACHE_SIZE; _indx_ += HAL_DCACHE_LINE_SIZE) { \
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126 asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); \
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127 } \
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128 CYG_MACRO_END
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129 #else
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130 // Synchronize the contents of the cache with memory.
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131 #define HAL_DCACHE_SYNC() \
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132 CYG_MACRO_START \
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133 cyg_int32 i; \
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134 cyg_uint32 *__base = (cyg_uint32 *) (0); \
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135 /* for (i = 0; i < HAL_DCACHE_SIZE; i += sizeof(cyg_uint32)) { */ \
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136 for (i = 0; i < (HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); i++, __base += HAL_DCACHE_LINE_SIZE/4){\
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137 asm volatile ("lwz %%r0,0(%0)" : : "r" (__base) : "r0"); \
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138 } \
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139 CYG_MACRO_END
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140 #endif
134
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141
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142 // Query the state of the data cache
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143 #define HAL_DCACHE_IS_ENABLED(_state_) \
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144 CYG_MACRO_START \
136
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145 (_state_) = 1; \
134
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146 CYG_MACRO_END
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147
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148 // Set the data cache refill burst size
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149 //#define HAL_DCACHE_BURST_SIZE(_size_)
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150
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151 // Set the data cache write mode
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152 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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153
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154 //#define HAL_DCACHE_WRITETHRU_MODE 0
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155 //#define HAL_DCACHE_WRITEBACK_MODE 1
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156
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157 // Load the contents of the given address range into the data cache
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158 // and then lock the cache so that it stays there.
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159 //#define HAL_DCACHE_LOCK(_base_, _size_)
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160
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161 // Undo a previous lock operation
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162 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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163
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164 // Unlock entire cache
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165 #define HAL_DCACHE_UNLOCK_ALL()
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166
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167 //-----------------------------------------------------------------------------
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168 // Data cache line control
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169
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170 // Allocate cache lines for the given address range without reading its
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171 // contents from memory.
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172 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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173
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174 // Write dirty cache lines to memory and invalidate the cache entries
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175 // for the given address range.
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176 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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177 CYG_MACRO_START \
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178 cyg_uint32 __base = (cyg_uint32) (_base_); \
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179 cyg_int32 __size = (cyg_int32) (_size_); \
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180 while (__size > 0) { \
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181 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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182 __base += HAL_DCACHE_LINE_SIZE; \
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183 __size -= HAL_DCACHE_LINE_SIZE; \
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184 } \
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185 CYG_MACRO_END
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186
134
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187 // Invalidate cache lines in the given range without writing to memory.
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188 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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189 CYG_MACRO_START \
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190 cyg_uint32 __base = (cyg_uint32) (_base_); \
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191 cyg_int32 __size = (cyg_int32) (_size_); \
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192 while (__size > 0) { \
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193 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
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194 __base += HAL_DCACHE_LINE_SIZE; \
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195 __size -= HAL_DCACHE_LINE_SIZE; \
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196 } \
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197 CYG_MACRO_END
134
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198
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199 // Write dirty cache lines to memory for the given address range.
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200 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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201 CYG_MACRO_START \
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202 cyg_uint32 __base = (cyg_uint32) (_base_); \
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203 cyg_int32 __size = (cyg_int32) (_size_); \
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204 while (__size > 0) { \
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205 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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206 __base += HAL_DCACHE_LINE_SIZE; \
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207 __size -= HAL_DCACHE_LINE_SIZE; \
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208 } \
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209 CYG_MACRO_END
134
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210
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211 // Preread the given range into the cache with the intention of reading
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212 // from it later.
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213 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
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214 CYG_MACRO_START \
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215 cyg_uint32 __base = (cyg_uint32) (_base_); \
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216 cyg_int32 __size = (cyg_int32) (_size_); \
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217 while (__size > 0) { \
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218 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
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219 __base += HAL_DCACHE_LINE_SIZE; \
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220 __size -= HAL_DCACHE_LINE_SIZE; \
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221 } \
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222 CYG_MACRO_END
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223
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224 // Preread the given range into the cache with the intention of writing
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225 // to it later.
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226 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
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227 CYG_MACRO_START \
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228 cyg_uint32 __base = (cyg_uint32) (_base_); \
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229 cyg_int32 __size = (cyg_int32) (_size_); \
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230 while (__size > 0) { \
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231 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
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232 __base += HAL_DCACHE_LINE_SIZE; \
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233 __size -= HAL_DCACHE_LINE_SIZE; \
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234 } \
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235 CYG_MACRO_END
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236
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237 // Allocate and zero the cache lines associated with the given range.
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238 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
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239 CYG_MACRO_START \
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240 cyg_uint32 __base = (cyg_uint32) (_base_); \
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241 cyg_int32 __size = (cyg_int32) (_size_); \
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242 while (__size > 0) { \
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243 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
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244 __base += HAL_DCACHE_LINE_SIZE; \
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245 __size -= HAL_DCACHE_LINE_SIZE; \
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246 } \
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247 CYG_MACRO_END
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248
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249 //-----------------------------------------------------------------------------
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250 // Global control of Instruction cache
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251
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252 // Enable the instruction cache
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253 #define HAL_ICACHE_ENABLE()
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254
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255 // Disable the instruction cache
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256 #define HAL_ICACHE_DISABLE()
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257
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258 // Invalidate the entire cache
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259 #define HAL_ICACHE_INVALIDATE_ALL() \
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260 CYG_MACRO_START \
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261 int _i_, _indx_; \
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262 _indx_ = 0; \
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263 for (_i_ = 0; _i_ < HAL_ICACHE_SETS; _i_++) { \
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264 asm volatile ("iccci 0,%0;" :: "r"(_indx_)); \
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265 _indx_ += HAL_ICACHE_LINE_SIZE; \
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266 } \
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267 CYG_MACRO_END
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268
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269 // Synchronize the contents of the cache with memory.
136
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270 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
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271
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272 // Query the state of the instruction cache
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273 #define HAL_ICACHE_IS_ENABLED(_state_) \
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274 CYG_MACRO_START \
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275 (_state_) = 1; \
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276 CYG_MACRO_END
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277
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278 // Set the instruction cache refill burst size
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279 //#define HAL_ICACHE_BURST_SIZE(_size_)
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280
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281 // Load the contents of the given address range into the instruction cache
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282 // and then lock the cache so that it stays there.
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283 //#define HAL_ICACHE_LOCK(_base_, _size_)
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284
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285 // Undo a previous lock operation
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286 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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287
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288 // Unlock entire cache
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289 #define HAL_ICACHE_UNLOCK_ALL()
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290
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291 //-----------------------------------------------------------------------------
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292 // Instruction cache line control
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293
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294 // Invalidate cache lines in the given range without writing to memory.
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295 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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296
1223
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297 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
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298 // Map a RAM address to a non-cached mirror
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299 #define CYGARC_UNCACHED_ADDRESS(p) ((unsigned long)(p) | 0x80000000)
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300 #else
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301 #define CYGARC_UNCACHED_ADDRESS(p) (p)
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302 #endif
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303
134
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304 //-----------------------------------------------------------------------------
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305 #endif // ifndef CYGONCE_VAR_CACHE_H
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306 // End of var_cache.h