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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents d8ce80bf8e90
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
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2 #define CYGONCE_HAL_PPC_QUICC_PPC8XX_H
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3
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4 //==========================================================================
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5 //
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6 // ppc8xx.h
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7 //
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8 // PowerPC QUICC register definitions
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9 //
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10 //==========================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 // Copyright (C) 2002, 2003 Gary Thomas
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16 //
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17 // eCos is free software; you can redistribute it and/or modify it under
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18 // the terms of the GNU General Public License as published by the Free
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19 // Software Foundation; either version 2 or (at your option) any later version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License along
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27 // with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use macros
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31 // or inline functions from this file, or you compile this file and link it
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32 // with other works to produce a work based on this file, this file does not
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33 // by itself cause the resulting work to be covered by the GNU General Public
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34 // License. However the source code for this file must still be made available
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35 // in accordance with section (3) of the GNU General Public License.
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36 //
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37 // This exception does not invalidate any other reasons why a work based on
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38 // this file might be covered by the GNU General Public License.
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39 //
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40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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41 // at http://sources.redhat.com/ecos/ecos-license/
208
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42 // -------------------------------------------
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43 //####ECOSGPLCOPYRIGHTEND####
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44 //==========================================================================
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45 //#####DESCRIPTIONBEGIN####
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46 //
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47 // Author(s): Red Hat
32
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48 // Contributors: hmt
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49 // Date: 1999-06-08
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50 // Purpose: Provide PPC QUICC definitions
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51 // Description: Provide PPC QUICC definitions
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52 // Usage: THIS IS NOT AN EXTERNAL API
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53 // This file is in the include dir to share it between
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54 // QUICC serial code and MBX initialization code.
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55 // #include <cyg/hal/quicc/ppc8xx.h>
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56 // ...
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57 //
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58 //
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59 //####DESCRIPTIONEND####
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60 //
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61 //==========================================================================
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62
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63 #ifdef __ASSEMBLER__
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64
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65 #define SIUMCR 0x000 /* SIU Module configuration */
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66 #define SYPCR 0x004 /* SIU System Protection Control */
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67 #define SIPEND 0x010 /* SIU Interrupt Pending Register */
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68 #define SIMASK 0x014 /* SIU Interrupt MASK Register */
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69 #define SIEL 0x018 /* SIU Interrupt Edge/Level Register */
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70 #define SIVEC 0x01C /* SIU Interrupt Vector Register */
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71 #define SDCR 0x030 /* SDMA Config Register */
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72 #define BR0 0x100 /* Base Register 0 */
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73 #define OR0 0x104 /* Option Register 0 */
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74 #define BR1 0x108 /* Base Register 1 */
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75 #define OR1 0x10C /* Option Register 1 */
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76 #define BR2 0x110 /* Base Register 2 */
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77 #define OR2 0x114 /* Option Register 2 */
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78 #define BR3 0x118 /* Base Register 2 */
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79 #define OR3 0x11C /* Option Register 2 */
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80 #define BR4 0x120 /* Base Register 2 */
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81 #define OR4 0x124 /* Option Register 2 */
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82 #define BR5 0x128 /* Base Register 2 */
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83 #define OR5 0x12C /* Option Register 2 */
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84 #define BR6 0x130 /* Base Register 2 */
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85 #define OR6 0x134 /* Option Register 2 */
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86 #define BR7 0x138 /* Base Register 2 */
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87 #define OR7 0x13C /* Option Register 2 */
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88 #define MAR 0x164 /* Memory Address */
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89 #define MCR 0x168 /* Memory Command */
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90 #define MAMR 0x170 /* Machine A Mode Register */
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91 #define MBMR 0x174 /* Machine B Mode Register */
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92 #define MPTPR 0x17A /* Memory Periodic Timer Prescaler */
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93 #define MDR 0x17C /* Memory Data */
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94 #define TBSCR 0x200 /* Time Base Status and Control Register */
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95 #define RTCSC 0x220 /* Real Timer Clock Status and Control */
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96 #define PISCR 0x240 /* PIT Status and Control */
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97 #define SCCR 0x280 /* System Clock Control Register */
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98 #define PLPRCR 0x284 /* PLL, Low power & Reset Control Register */
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99 #define RTCSCK 0x320
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100 #define RTCK 0x324
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101 #define RTSECK 0x328
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102 #define RTCALK 0x32C
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103 #define PADIR 0x950 /* Port A - Pin direction */
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104 #define PAPAR 0x952 /* Port A - Pin assignment */
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105 #define PAODR 0x954 /* Port A - Open Drain Control */
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106 #define PADAT 0x956 /* Port A - Data */
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107
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108 #else
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109
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110 #include <cyg/infra/cyg_type.h>
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111
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112 /*****************************************************************
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113 Communications Processor Buffer Descriptor
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114 *****************************************************************/
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115 struct cp_bufdesc {
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116 volatile unsigned short ctrl; /* status/control register */
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117 volatile unsigned short length; /* buffer length */
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118 volatile char *buffer; /* buffer pointer */
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119 };
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120
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121 /*****************************************************************
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122 HDLC parameter RAM
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123 *****************************************************************/
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124
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125 struct hdlc_pram {
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126 /*
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127 * SCC parameter RAM
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128 */
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129 unsigned short rbase; /* RX BD base address */
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130 unsigned short tbase; /* TX BD base address */
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131 unsigned char rfcr; /* Rx function code */
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132 unsigned char tfcr; /* Tx function code */
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133 unsigned short mrblr; /* Rx buffer length */
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134 unsigned long rstate; /* Rx internal state */
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135 unsigned long rptr; /* Rx internal data pointer */
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136 unsigned short rbptr; /* rb BD Pointer */
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137 unsigned short rcount; /* Rx internal byte count */
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138 unsigned long rtemp; /* Rx temp */
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139 unsigned long tstate; /* Tx internal state */
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140 unsigned long tptr; /* Tx internal data pointer */
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141 unsigned short tbptr; /* Tx BD pointer */
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142 unsigned short tcount; /* Tx byte count */
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143 unsigned long ttemp; /* Tx temp */
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144 unsigned long rcrc; /* temp receive CRC */
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145 unsigned long tcrc; /* temp transmit CRC */
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146
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147 /*
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148 * HDLC specific parameter RAM
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149 */
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150 unsigned char RSRVD1[4];
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151 unsigned long c_mask; /* CRC constant */
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152 unsigned long c_pres; /* CRC preset */
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153 unsigned short disfc; /* discarded frame counter */
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154 unsigned short crcec; /* CRC error counter */
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155 unsigned short abtsc; /* abort sequence counter */
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156 unsigned short nmarc; /* nonmatching address rx cnt */
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157 unsigned short retrc; /* frame retransmission cnt */
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158 unsigned short mflr; /* maximum frame length reg */
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159 unsigned short max_cnt; /* maximum length counter */
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160 unsigned short rfthr; /* received frames threshold */
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161 unsigned short rfcnt; /* received frames count */
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162 unsigned short hmask; /* user defined frm addr mask */
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163 unsigned short haddr1; /* user defined frm address 1 */
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164 unsigned short haddr2; /* user defined frm address 2 */
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165 unsigned short haddr3; /* user defined frm address 3 */
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166 unsigned short haddr4; /* user defined frm address 4 */
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167 unsigned short tmp; /* temp */
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168 unsigned short tmp_mb; /* temp */
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169 };
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170
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171
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172 /*****************************************************************
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173 ASYNC HDLC parameter RAM
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174 *****************************************************************/
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175
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176 struct async_hdlc_pram {
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177 /*
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178 * SCC parameter RAM
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179 */
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180 unsigned short rbase; /* RX BD base address */
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181 unsigned short tbase; /* TX BD base address */
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182 unsigned char rfcr; /* Rx function code */
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183 unsigned char tfcr; /* Tx function code */
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184 unsigned short mrblr; /* Rx buffer length */
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185 unsigned long rstate; /* Rx internal state */
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186 unsigned long rptr; /* Rx internal data pointer */
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187 unsigned short rbptr; /* rb BD Pointer */
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188 unsigned short rcount; /* Rx internal byte count */
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189 unsigned long rtemp; /* Rx temp */
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190 unsigned long tstate; /* Tx internal state */
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191 unsigned long tptr; /* Tx internal data pointer */
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192 unsigned short tbptr; /* Tx BD pointer */
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193 unsigned short tcount; /* Tx byte count */
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194 unsigned long ttemp; /* Tx temp */
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195 unsigned long rcrc; /* temp receive CRC */
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196 unsigned long tcrc; /* temp transmit CRC */
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197
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198 /*
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199 * ASYNC HDLC specific parameter RAM
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200 */
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201 unsigned char RSRVD1[4];
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202 unsigned long c_mask; /* CRC constant */
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203 unsigned long c_pres; /* CRC preset */
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204 unsigned short bof; /* begining of flag character */
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205 unsigned short eof; /* end of flag character */
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206 unsigned short esc; /* control escape character */
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207 unsigned char RSRVD2[4];
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208 unsigned short zero; /* zero */
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209 unsigned char RSRVD3[2];
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210 unsigned short rfthr; /* received frames threshold */
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211 unsigned char RSRVD4[4];
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212 unsigned long txctl_tbl; /* Tx ctl char mapping table */
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213 unsigned long rxctl_tbl; /* Rx ctl char mapping table */
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214 unsigned short nof; /* Number of opening flags */
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215 };
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216
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217
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218 /*****************************************************************
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219 UART parameter RAM
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220 *****************************************************************/
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221
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222 /*
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223 * bits in uart control characters table
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224 */
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225 #define CC_INVALID 0x8000 /* control character is valid */
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226 #define CC_REJ 0x4000 /* don't store char in buffer */
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227 #define CC_CHAR 0x00ff /* control character */
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228
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229 /* UART */
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230 struct uart_pram {
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231 /*
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232 * SCC parameter RAM
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233 */
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234 unsigned short rbase; /* RX BD base address */
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235 unsigned short tbase; /* TX BD base address */
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236 unsigned char rfcr; /* Rx function code */
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237 unsigned char tfcr; /* Tx function code */
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238 unsigned short mrblr; /* Rx buffer length */
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239 unsigned long rstate; /* Rx internal state */
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240 unsigned long rptr; /* Rx internal data pointer */
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241 unsigned short rbptr; /* rb BD Pointer */
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242 unsigned short rcount; /* Rx internal byte count */
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243 unsigned long rx_temp; /* Rx temp */
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244 unsigned long tstate; /* Tx internal state */
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245 unsigned long tptr; /* Tx internal data pointer */
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246 unsigned short tbptr; /* Tx BD pointer */
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247 unsigned short tcount; /* Tx byte count */
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248 unsigned long ttemp; /* Tx temp */
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249 unsigned long rcrc; /* temp receive CRC */
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250 unsigned long tcrc; /* temp transmit CRC */
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251
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252 /*
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253 * UART specific parameter RAM
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254 */
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255 unsigned char RSRVD1[8];
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256 unsigned short max_idl; /* maximum idle characters */
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257 unsigned short idlc; /* rx idle counter (internal) */
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258 unsigned short brkcr; /* break count register */
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259
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260 unsigned short parec; /* Rx parity error counter */
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261 unsigned short frmer; /* Rx framing error counter */
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262 unsigned short nosec; /* Rx noise counter */
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263 unsigned short brkec; /* Rx break character counter */
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264 unsigned short brkln; /* Reaceive break length */
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265
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266 unsigned short uaddr1; /* address character 1 */
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267 unsigned short uaddr2; /* address character 2 */
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268 unsigned short rtemp; /* temp storage */
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269 unsigned short toseq; /* Tx out of sequence char */
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270 unsigned short cc[8]; /* Rx control characters */
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271 unsigned short rccm; /* Rx control char mask */
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272 unsigned short rccr; /* Rx control char register */
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273 unsigned short rlbc; /* Receive last break char */
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274 };
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275
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276
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277
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278 /*****************************************************************
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279 BISYNC parameter RAM
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280 *****************************************************************/
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281
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282 struct bisync_pram {
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283 /*
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284 * SCC parameter RAM
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285 */
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286 unsigned short rbase; /* RX BD base address */
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287 unsigned short tbase; /* TX BD base address */
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288 unsigned char rfcr; /* Rx function code */
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289 unsigned char tfcr; /* Tx function code */
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290 unsigned short mrblr; /* Rx buffer length */
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291 unsigned long rstate; /* Rx internal state */
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292 unsigned long rptr; /* Rx internal data pointer */
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293 unsigned short rbptr; /* rb BD Pointer */
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294 unsigned short rcount; /* Rx internal byte count */
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295 unsigned long rtemp; /* Rx temp */
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296 unsigned long tstate; /* Tx internal state */
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297 unsigned long tptr; /* Tx internal data pointer */
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298 unsigned short tbptr; /* Tx BD pointer */
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299 unsigned short tcount; /* Tx byte count */
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300 unsigned long ttemp; /* Tx temp */
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301 unsigned long rcrc; /* temp receive CRC */
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302 unsigned long tcrc; /* temp transmit CRC */
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303
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304 /*
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305 * BISYNC specific parameter RAM
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306 */
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307 unsigned char RSRVD1[4];
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308 unsigned long crcc; /* CRC Constant Temp Value */
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309 unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
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310 unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
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311 unsigned short parec; /* Receive Parity Error Counter */
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312 unsigned short bsync; /* BISYNC SYNC Character */
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313 unsigned short bdle; /* BISYNC DLE Character */
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314 unsigned short cc[8]; /* Rx control characters */
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315 unsigned short rccm; /* Receive Control Character Mask */
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316 };
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317
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318 /*****************************************************************
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319 IOM2 parameter RAM
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320 (overlaid on tx bd[5] of SCC channel[2])
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321 *****************************************************************/
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322 struct iom2_pram {
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323 unsigned short ci_data; /* ci data */
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324 unsigned short monitor_data; /* monitor data */
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325 unsigned short tstate; /* transmitter state */
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326 unsigned short rstate; /* receiver state */
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327 };
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328
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329 /*****************************************************************
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330 SPI/SMC parameter RAM
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331 (overlaid on tx bd[6,7] of SCC channel[2])
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332 *****************************************************************/
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333
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334 #define SPI_R 0x8000 /* Ready bit in BD */
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335
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336 struct spi_pram {
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337 unsigned short rbase; /* Rx BD Base Address */
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338 unsigned short tbase; /* Tx BD Base Address */
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339 unsigned char rfcr; /* Rx function code */
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340 unsigned char tfcr; /* Tx function code */
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341 unsigned short mrblr; /* Rx buffer length */
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342 unsigned long rstate; /* Rx internal state */
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343 unsigned long rptr; /* Rx internal data pointer */
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344 unsigned short rbptr; /* rb BD Pointer */
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345 unsigned short rcount; /* Rx internal byte count */
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346 unsigned long rtemp; /* Rx temp */
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347 unsigned long tstate; /* Tx internal state */
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348 unsigned long tptr; /* Tx internal data pointer */
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349 unsigned short tbptr; /* Tx BD pointer */
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350 unsigned short tcount; /* Tx byte count */
1564
d8ce80bf8e90 * include/ppc8xx.h: Add definition for 8 bytes to spi_pram structure
asl
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351 unsigned long ttemp[2]; /* Tx temp */
d8ce80bf8e90 * include/ppc8xx.h: Add definition for 8 bytes to spi_pram structure
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352 unsigned short rpbase; /* Relocated param block pointer */
d8ce80bf8e90 * include/ppc8xx.h: Add definition for 8 bytes to spi_pram structure
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353 unsigned short res; /* unused */
32
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354 };
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355
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356 struct smc_uart_pram {
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357 unsigned short rbase; /* Rx BD Base Address */
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358 unsigned short tbase; /* Tx BD Base Address */
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359 unsigned char rfcr; /* Rx function code */
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360 unsigned char tfcr; /* Tx function code */
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361 unsigned short mrblr; /* Rx buffer length */
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362 unsigned long rstate; /* Rx internal state */
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363 unsigned long rptr; /* Rx internal data pointer */
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364 unsigned short rbptr; /* rb BD Pointer */
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365 unsigned short rcount; /* Rx internal byte count */
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366 unsigned long rtemp; /* Rx temp */
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367 unsigned long tstate; /* Tx internal state */
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368 unsigned long tptr; /* Tx internal data pointer */
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369 unsigned short tbptr; /* Tx BD pointer */
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370 unsigned short tcount; /* Tx byte count */
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371 unsigned long ttemp; /* Tx temp */
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372 unsigned short max_idl; /* Maximum IDLE Characters */
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373 unsigned short idlc; /* Temporary IDLE Counter */
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374 unsigned short brkln; /* Last Rx Break Length */
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375 unsigned short brkec; /* Rx Break Condition Counter */
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376 unsigned short brkcr; /* Break Count Register (Tx) */
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377 unsigned short r_mask; /* Temporary bit mask */
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378 };
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379
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380 struct smc_trnsp_pram {
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381 unsigned short rbase; /* Rx BD Base Address */
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382 unsigned short tbase; /* Tx BD Base Address */
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383 unsigned char rfcr; /* Rx function code */
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384 unsigned char tfcr; /* Tx function code */
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385 unsigned short mrblr; /* Rx buffer length */
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386 unsigned long rstate; /* Rx internal state */
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387 unsigned long rptr; /* Rx internal data pointer */
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388 unsigned short rbptr; /* rb BD Pointer */
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389 unsigned short rcount; /* Rx internal byte count */
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390 unsigned long rtemp; /* Rx temp */
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391 unsigned long tstate; /* Tx internal state */
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392 unsigned long tptr; /* Tx internal data pointer */
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393 unsigned short tbptr; /* Tx BD pointer */
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394 unsigned short tcount; /* Tx byte count */
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395 unsigned long ttemp; /* Tx temp */
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396 unsigned short RSRVD[5]; /* RSRVD */
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397 };
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398
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399 struct centronics_pram {
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400 unsigned short rbase; /* Rx BD Base Address */
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401 unsigned short tbase; /* Tx BD Base Address */
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402 unsigned char fcr; /* function code */
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403 unsigned char smask; /* Status Mask */
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404 unsigned short mrblr; /* Rx buffer length */
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405 unsigned long rstate; /* Rx internal state */
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406 unsigned long rptr; /* Rx internal data pointer */
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407 unsigned short rbptr; /* rb BD Pointer */
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408 unsigned short rcount; /* Rx internal byte count */
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409 unsigned long rtemp; /* Rx temp */
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410 unsigned long tstate; /* Tx internal state */
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411 unsigned long tptr; /* Tx internal data pointer */
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412 unsigned short tbptr; /* Tx BD pointer */
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413 unsigned short tcount; /* Tx byte count */
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414 unsigned long ttemp; /* Tx temp */
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415 unsigned short max_sl; /* Maximum Silence period */
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416 unsigned short sl_cnt; /* Silence Counter */
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417 unsigned short char1; /* CONTROL char 1 */
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418 unsigned short char2; /* CONTROL char 2 */
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419 unsigned short char3; /* CONTROL char 3 */
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420 unsigned short char4; /* CONTROL char 4 */
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421 unsigned short char5; /* CONTROL char 5 */
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422 unsigned short char6; /* CONTROL char 6 */
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423 unsigned short char7; /* CONTROL char 7 */
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424 unsigned short char8; /* CONTROL char 8 */
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425 unsigned short rccm; /* Rx Control Char Mask */
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426 unsigned short rccr; /* Rx Char Control Register */
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427 };
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428
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429 struct idma_pram {
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430 unsigned short ibase; /* IDMA BD Base Address */
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431 unsigned short ibptr; /* IDMA buffer descriptor pointer */
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432 unsigned long istate; /* IDMA internal state */
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jlarmour
parents:
diff changeset
433 unsigned long itemp; /* IDMA temp */
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jlarmour
parents:
diff changeset
434 };
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jlarmour
parents:
diff changeset
435
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jlarmour
parents:
diff changeset
436 struct ethernet_pram {
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jlarmour
parents:
diff changeset
437 /*
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jlarmour
parents:
diff changeset
438 * SCC parameter RAM
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jlarmour
parents:
diff changeset
439 */
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jlarmour
parents:
diff changeset
440 unsigned short rbase; /* RX BD base address */
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jlarmour
parents:
diff changeset
441 unsigned short tbase; /* TX BD base address */
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jlarmour
parents:
diff changeset
442 unsigned char rfcr; /* Rx function code */
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jlarmour
parents:
diff changeset
443 unsigned char tfcr; /* Tx function code */
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jlarmour
parents:
diff changeset
444 unsigned short mrblr; /* Rx buffer length */
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jlarmour
parents:
diff changeset
445 unsigned long rstate; /* Rx internal state */
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jlarmour
parents:
diff changeset
446 unsigned long rptr; /* Rx internal data pointer */
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jlarmour
parents:
diff changeset
447 unsigned short rbptr; /* rb BD Pointer */
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jlarmour
parents:
diff changeset
448 unsigned short rcount; /* Rx internal byte count */
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jlarmour
parents:
diff changeset
449 unsigned long rtemp; /* Rx temp */
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jlarmour
parents:
diff changeset
450 unsigned long tstate; /* Tx internal state */
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jlarmour
parents:
diff changeset
451 unsigned long tptr; /* Tx internal data pointer */
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jlarmour
parents:
diff changeset
452 unsigned short tbptr; /* Tx BD pointer */
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jlarmour
parents:
diff changeset
453 unsigned short tcount; /* Tx byte count */
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jlarmour
parents:
diff changeset
454 unsigned long ttemp; /* Tx temp */
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jlarmour
parents:
diff changeset
455 unsigned long rcrc; /* temp receive CRC */
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jlarmour
parents:
diff changeset
456 unsigned long tcrc; /* temp transmit CRC */
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jlarmour
parents:
diff changeset
457
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jlarmour
parents:
diff changeset
458 /*
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jlarmour
parents:
diff changeset
459 * ETHERNET specific parameter RAM
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jlarmour
parents:
diff changeset
460 */
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jlarmour
parents:
diff changeset
461 unsigned long c_pres; /* preset CRC */
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jlarmour
parents:
diff changeset
462 unsigned long c_mask; /* constant mask for CRC */
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jlarmour
parents:
diff changeset
463 unsigned long crcec; /* CRC error counter */
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jlarmour
parents:
diff changeset
464 unsigned long alec; /* alighnment error counter */
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jlarmour
parents:
diff changeset
465 unsigned long disfc; /* discard frame counter */
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jlarmour
parents:
diff changeset
466 unsigned short pads; /* short frame PAD characters */
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jlarmour
parents:
diff changeset
467 unsigned short ret_lim; /* retry limit threshold */
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jlarmour
parents:
diff changeset
468 unsigned short ret_cnt; /* retry limit counter */
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jlarmour
parents:
diff changeset
469 unsigned short mflr; /* maximum frame length reg */
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jlarmour
parents:
diff changeset
470 unsigned short minflr; /* minimum frame length reg */
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jlarmour
parents:
diff changeset
471 unsigned short maxd1; /* maximum DMA1 length reg */
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jlarmour
parents:
diff changeset
472 unsigned short maxd2; /* maximum DMA2 length reg */
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jlarmour
parents:
diff changeset
473 unsigned short maxd; /* rx max DMA */
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jlarmour
parents:
diff changeset
474 unsigned short dma_cnt; /* rx dma counter */
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jlarmour
parents:
diff changeset
475 unsigned short max_b; /* max bd byte count */
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jlarmour
parents:
diff changeset
476 unsigned short gaddr1; /* group address filter 1 */
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jlarmour
parents:
diff changeset
477 unsigned short gaddr2; /* group address filter 2 */
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jlarmour
parents:
diff changeset
478 unsigned short gaddr3; /* group address filter 3 */
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jlarmour
parents:
diff changeset
479 unsigned short gaddr4; /* group address filter 4 */
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jlarmour
parents:
diff changeset
480 unsigned long tbuf0_data0; /* save area 0 - current frm */
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parents:
diff changeset
481 unsigned long tbuf0_data1; /* save area 1 - current frm */
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jlarmour
parents:
diff changeset
482 unsigned long tbuf0_rba0;
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jlarmour
parents:
diff changeset
483 unsigned long tbuf0_crc;
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jlarmour
parents:
diff changeset
484 unsigned short tbuf0_bcnt;
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jlarmour
parents:
diff changeset
485 unsigned short paddr_h; /* physical address (MSB) */
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jlarmour
parents:
diff changeset
486 unsigned short paddr_m; /* physical address */
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jlarmour
parents:
diff changeset
487 unsigned short paddr_l; /* physical address (LSB) */
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jlarmour
parents:
diff changeset
488 unsigned short p_per; /* persistence */
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jlarmour
parents:
diff changeset
489 unsigned short rfbd_ptr; /* rx first bd pointer */
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jlarmour
parents:
diff changeset
490 unsigned short tfbd_ptr; /* tx first bd pointer */
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jlarmour
parents:
diff changeset
491 unsigned short tlbd_ptr; /* tx last bd pointer */
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jlarmour
parents:
diff changeset
492 unsigned long tbuf1_data0; /* save area 0 - next frame */
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jlarmour
parents:
diff changeset
493 unsigned long tbuf1_data1; /* save area 1 - next frame */
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jlarmour
parents:
diff changeset
494 unsigned long tbuf1_rba0;
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jlarmour
parents:
diff changeset
495 unsigned long tbuf1_crc;
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jlarmour
parents:
diff changeset
496 unsigned short tbuf1_bcnt;
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jlarmour
parents:
diff changeset
497 unsigned short tx_len; /* tx frame length counter */
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jlarmour
parents:
diff changeset
498 unsigned short iaddr1; /* individual address filter 1*/
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jlarmour
parents:
diff changeset
499 unsigned short iaddr2; /* individual address filter 2*/
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jlarmour
parents:
diff changeset
500 unsigned short iaddr3; /* individual address filter 3*/
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jlarmour
parents:
diff changeset
501 unsigned short iaddr4; /* individual address filter 4*/
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jlarmour
parents:
diff changeset
502 unsigned short boff_cnt; /* back-off counter */
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jlarmour
parents:
diff changeset
503 unsigned short taddr_h; /* temp address (MSB) */
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jlarmour
parents:
diff changeset
504 unsigned short taddr_m; /* temp address */
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jlarmour
parents:
diff changeset
505 unsigned short taddr_l; /* temp address (LSB) */
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jlarmour
parents:
diff changeset
506 };
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jlarmour
parents:
diff changeset
507
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jlarmour
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diff changeset
508 struct transparent_pram {
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jlarmour
parents:
diff changeset
509 /*
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jlarmour
parents:
diff changeset
510 * SCC parameter RAM
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jlarmour
parents:
diff changeset
511 */
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jlarmour
parents:
diff changeset
512 unsigned short rbase; /* RX BD base address */
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jlarmour
parents:
diff changeset
513 unsigned short tbase; /* TX BD base address */
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jlarmour
parents:
diff changeset
514 unsigned char rfcr; /* Rx function code */
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jlarmour
parents:
diff changeset
515 unsigned char tfcr; /* Tx function code */
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jlarmour
parents:
diff changeset
516 unsigned short mrblr; /* Rx buffer length */
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jlarmour
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diff changeset
517 unsigned long rstate; /* Rx internal state */
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jlarmour
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diff changeset
518 unsigned long rptr; /* Rx internal data pointer */
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jlarmour
parents:
diff changeset
519 unsigned short rbptr; /* rb BD Pointer */
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jlarmour
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diff changeset
520 unsigned short rcount; /* Rx internal byte count */
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jlarmour
parents:
diff changeset
521 unsigned long rtemp; /* Rx temp */
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jlarmour
parents:
diff changeset
522 unsigned long tstate; /* Tx internal state */
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jlarmour
parents:
diff changeset
523 unsigned long tptr; /* Tx internal data pointer */
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jlarmour
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diff changeset
524 unsigned short tbptr; /* Tx BD pointer */
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jlarmour
parents:
diff changeset
525 unsigned short tcount; /* Tx byte count */
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jlarmour
parents:
diff changeset
526 unsigned long ttemp; /* Tx temp */
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jlarmour
parents:
diff changeset
527 unsigned long rcrc; /* temp receive CRC */
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jlarmour
parents:
diff changeset
528 unsigned long tcrc; /* temp transmit CRC */
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jlarmour
parents:
diff changeset
529
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jlarmour
parents:
diff changeset
530 /*
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jlarmour
parents:
diff changeset
531 * TRANSPARENT specific parameter RAM
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jlarmour
parents:
diff changeset
532 */
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jlarmour
parents:
diff changeset
533 unsigned long crc_p; /* CRC Preset */
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jlarmour
parents:
diff changeset
534 unsigned long crc_c; /* CRC constant */
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jlarmour
parents:
diff changeset
535 };
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jlarmour
parents:
diff changeset
536
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jlarmour
parents:
diff changeset
537 struct timer_pram {
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jlarmour
parents:
diff changeset
538 /*
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jlarmour
parents:
diff changeset
539 * RISC timers parameter RAM
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jlarmour
parents:
diff changeset
540 */
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jlarmour
parents:
diff changeset
541 unsigned short tm_base; /* RISC timer table base adr */
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jlarmour
parents:
diff changeset
542 unsigned short tm_ptr; /* RISC timer table pointer */
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jlarmour
parents:
diff changeset
543 unsigned short r_tmr; /* RISC timer mode register */
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jlarmour
parents:
diff changeset
544 unsigned short r_tmv; /* RISC timer valid register */
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jlarmour
parents:
diff changeset
545 unsigned long tm_cmd; /* RISC timer cmd register */
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jlarmour
parents:
diff changeset
546 unsigned long tm_cnt; /* RISC timer internal cnt */
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jlarmour
parents:
diff changeset
547 };
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jlarmour
parents:
diff changeset
548
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jlarmour
parents:
diff changeset
549 struct ucode_pram {
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jlarmour
parents:
diff changeset
550 /*
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jlarmour
parents:
diff changeset
551 * RISC ucode parameter RAM
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jlarmour
parents:
diff changeset
552 */
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jlarmour
parents:
diff changeset
553 unsigned short rev_num; /* Ucode Revision Number */
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jlarmour
parents:
diff changeset
554 unsigned short d_ptr; /* MISC Dump area pointer */
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jlarmour
parents:
diff changeset
555 unsigned long temp1; /* MISC Temp1 */
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jlarmour
parents:
diff changeset
556 unsigned long temp2; /* MISC Temp2 */
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jlarmour
parents:
diff changeset
557 };
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jlarmour
parents:
diff changeset
558
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jlarmour
parents:
diff changeset
559 struct i2c_pram {
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jlarmour
parents:
diff changeset
560 /*
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jlarmour
parents:
diff changeset
561 * I2C parameter RAM
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jlarmour
parents:
diff changeset
562 */
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jlarmour
parents:
diff changeset
563 unsigned short rbase; /* RX BD base address */
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jlarmour
parents:
diff changeset
564 unsigned short tbase; /* TX BD base address */
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jlarmour
parents:
diff changeset
565 unsigned char rfcr; /* Rx function code */
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jlarmour
parents:
diff changeset
566 unsigned char tfcr; /* Tx function code */
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jlarmour
parents:
diff changeset
567 unsigned short mrblr; /* Rx buffer length */
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jlarmour
parents:
diff changeset
568 unsigned long rstate; /* Rx internal state */
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jlarmour
parents:
diff changeset
569 unsigned long rptr; /* Rx internal data pointer */
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jlarmour
parents:
diff changeset
570 unsigned short rbptr; /* rb BD Pointer */
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jlarmour
parents:
diff changeset
571 unsigned short rcount; /* Rx internal byte count */
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jlarmour
parents:
diff changeset
572 unsigned long rtemp; /* Rx temp */
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jlarmour
parents:
diff changeset
573 unsigned long tstate; /* Tx internal state */
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jlarmour
parents:
diff changeset
574 unsigned long tptr; /* Tx internal data pointer */
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jlarmour
parents:
diff changeset
575 unsigned short tbptr; /* Tx BD pointer */
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jlarmour
parents:
diff changeset
576 unsigned short tcount; /* Tx byte count */
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
577 unsigned long ttemp[2]; /* Tx temp */
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parents: 66
diff changeset
578 unsigned short rpbase; /* Relocated param block pointer */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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diff changeset
579 unsigned short res; /* unused */
32
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diff changeset
580 };
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diff changeset
581
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parents:
diff changeset
582 /*
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jlarmour
parents:
diff changeset
583 * definitions of EPPC memory structures
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parents:
diff changeset
584 */
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parents:
diff changeset
585 typedef struct eppc {
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diff changeset
586 /* BASE + 0x0000: INTERNAL REGISTERS */
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diff changeset
587
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parents:
diff changeset
588 /* SIU */
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diff changeset
589 volatile unsigned long siu_mcr; /* module configuration reg */
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590 volatile unsigned long siu_sypcr; /* System protection cnt */
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diff changeset
591 unsigned char RSRVD58[0x6];
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diff changeset
592 volatile unsigned short siu_swsr; /* sw service */
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diff changeset
593 volatile unsigned long siu_sipend; /* Interrupt pend reg */
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parents:
diff changeset
594 volatile unsigned long siu_simask; /* Interrupt mask reg */
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parents:
diff changeset
595 volatile unsigned long siu_siel; /* Interrupt edge level mask reg */
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diff changeset
596 volatile unsigned long siu_sivec; /* Interrupt vector */
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diff changeset
597 volatile unsigned long siu_tesr; /* Transfer error status */
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diff changeset
598 volatile unsigned char RSRVD1[0xc];
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diff changeset
599 volatile unsigned long dma_sdcr; /* SDMA configuration reg */
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diff changeset
600 unsigned char RSRVD55[0x4c];
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parents:
diff changeset
601
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parents:
diff changeset
602 /* PCMCIA */
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diff changeset
603 volatile unsigned long pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
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diff changeset
604 volatile unsigned long pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
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605 volatile unsigned long pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
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606 volatile unsigned long pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
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parents:
diff changeset
607 volatile unsigned long pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
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parents:
diff changeset
608 volatile unsigned long pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
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609 volatile unsigned long pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
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diff changeset
610 volatile unsigned long pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
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611 volatile unsigned long pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
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612 volatile unsigned long pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
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613 volatile unsigned long pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
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diff changeset
614 volatile unsigned long pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
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615 volatile unsigned long pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
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616 volatile unsigned long pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
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617 volatile unsigned long pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
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618 volatile unsigned long pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
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619 volatile unsigned char RSRVD2[0x20];
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620 volatile unsigned long pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
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621 volatile unsigned long pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
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622 volatile unsigned long pcmcia_pscr; /* PCMCIA Status Reg */
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diff changeset
623 volatile unsigned char RSRVD2a[0x4];
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624 volatile unsigned long pcmcia_pipr; /* PCMCIA Pins Value Reg */
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625 volatile unsigned char RSRVD2b[0x4];
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626 volatile unsigned long pcmcia_per; /* PCMCIA Enable Reg */
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diff changeset
627 volatile unsigned char RSRVD2c[0x4];
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628
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diff changeset
629 /* MEMC */
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630 volatile unsigned long memc_br0; /* base register 0 */
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diff changeset
631 volatile unsigned long memc_or0; /* option register 0 */
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diff changeset
632 volatile unsigned long memc_br1; /* base register 1 */
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633 volatile unsigned long memc_or1; /* option register 1 */
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634 volatile unsigned long memc_br2; /* base register 2 */
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635 volatile unsigned long memc_or2; /* option register 2 */
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636 volatile unsigned long memc_br3; /* base register 3 */
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637 volatile unsigned long memc_or3; /* option register 3 */
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638 volatile unsigned long memc_br4; /* base register 3 */
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diff changeset
639 volatile unsigned long memc_or4; /* option register 3 */
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640 volatile unsigned long memc_br5; /* base register 3 */
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641 volatile unsigned long memc_or5; /* option register 3 */
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642 volatile unsigned long memc_br6; /* base register 3 */
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643 volatile unsigned long memc_or6; /* option register 3 */
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644 volatile unsigned long memc_br7; /* base register 3 */
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645 volatile unsigned long memc_or7; /* option register 3 */
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646 volatile unsigned char RSRVD3[0x24];
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647 volatile unsigned long memc_mar; /* Memory address */
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diff changeset
648 volatile unsigned long memc_mcr; /* Memory command */
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649 volatile unsigned char RSRVD4[0x4];
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diff changeset
650 volatile unsigned long memc_mamr; /* Machine A mode */
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651 volatile unsigned long memc_mbmr; /* Machine B mode */
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652 volatile unsigned short memc_mstat; /* Memory status */
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653 volatile unsigned short memc_mptpr; /* Memory preidic timer prescalar */
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654 volatile unsigned long memc_mdr; /* Memory data */
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diff changeset
655 volatile unsigned char RSRVD5[0x80];
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656
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657 /* SYSTEM INTEGRATION TIMERS */
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658 volatile unsigned short simt_tbscr; /* Time base stat&ctr */
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659 volatile unsigned char RSRVD100[0x2];
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660 volatile unsigned long simt_tbreff0; /* Time base reference 0 */
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661 volatile unsigned long simt_tbreff1; /* Time base reference 1 */
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662 volatile unsigned char RSRVD6[0x14];
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663 volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */
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664 volatile unsigned char RSRVD110[0x2];
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665 volatile unsigned long simt_rtc; /* Realtime clock */
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666 volatile unsigned long simt_rtsec; /* Realtime alarm seconds */
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667 volatile unsigned long simt_rtcal; /* Realtime alarm */
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668 volatile unsigned char RSRVD56[0x10];
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669 volatile unsigned long simt_piscr; /* PIT stat&ctrl */
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670 volatile unsigned long simt_pitc; /* PIT counter */
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671 volatile unsigned long simt_pitr; /* PIT */
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672 volatile unsigned char RSRVD7[0x34];
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673
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674 /* CLOCKS, RESET */
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diff changeset
675 volatile unsigned long clkr_sccr; /* System clk cntrl */
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676 volatile unsigned long clkr_plprcr; /* PLL reset&ctrl */
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677 volatile unsigned long clkr_rsr; /* reset status */
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678 volatile unsigned char RSRVD66a[0x74];
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679
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680 /* System Integration Timers Keys */
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681 volatile unsigned long simt_tbscrk; /* Timebase Status&Ctrl Key */
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682 volatile unsigned long simt_tbreff0k; /* Timebase Reference 0 Key */
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683 volatile unsigned long simt_tbreff1k; /* Timebase Reference 1 Key */
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684 volatile unsigned long simt_tbk; /* Timebase and Decrementer Key */
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685 volatile unsigned char RSRVD66b[0x10];
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686 volatile unsigned long simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
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687 volatile unsigned long simt_rtck; /* Real-Time Clock Key */
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688 volatile unsigned long simt_rtseck; /* Real-Time Alarm Seconds Key */
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689 volatile unsigned long simt_rtcalk; /* Real-Time Alarm Key */
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diff changeset
690 volatile unsigned char RSRVD66c[0x10];
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diff changeset
691 volatile unsigned long simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
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diff changeset
692 volatile unsigned long simt_pitck; /* Periodic Interrupt Count Key */
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diff changeset
693 volatile unsigned char RSRVD66d[0x38];
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diff changeset
694
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695
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diff changeset
696 /* Clock and Reset Keys */
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697 volatile unsigned long clkr_sccrk; /* System Clock Control Key */
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698 volatile unsigned long clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
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699 volatile unsigned long clkr_rsrk; /* Reset Status Key */
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diff changeset
700 volatile unsigned char RSRVD66e[0x4b4];
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diff changeset
701
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702 volatile unsigned long lcd_lccr; /* configuration Reg */
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703 volatile unsigned long lcd_lchcr; /* Horizontal ctl Reg */
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704 volatile unsigned long lcd_lcvcr; /* Vertical ctl Reg */
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705 unsigned char RSRVD67[4];
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706 volatile unsigned long lcd_lcfaa; /* Frame buffer A Address */
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diff changeset
707 volatile unsigned long lcd_lcfba; /* Frame buffer B Address */
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708 volatile unsigned char lcd_lcsr; /* Status Reg */
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709 volatile unsigned char RSRVD9[0x7];
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diff changeset
710
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diff changeset
711 /* I2C */
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diff changeset
712 volatile unsigned char i2c_i2mod; /* i2c mode */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
713 unsigned char RSRVD59[3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
714 volatile unsigned char i2c_i2add; /* i2c address */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
715 unsigned char RSRVD60[3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
716 volatile unsigned char i2c_i2brg; /* i2c brg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
717 unsigned char RSRVD61[3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
718 volatile unsigned char i2c_i2com; /* i2c command */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
719 unsigned char RSRVD62[3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
720 volatile unsigned char i2c_i2cer; /* i2c event */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
721 unsigned char RSRVD63[3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
722 volatile unsigned char i2c_i2cmr; /* i2c mask */
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
723 volatile unsigned char RSRVD10[0x0b];
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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parents: 66
diff changeset
724 volatile unsigned char i2c_spare_pram[0x80]; /* Used by patched ucode */
32
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
725
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
726 /* DMA */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
727 volatile unsigned char RSRVD11[0x4];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
728 volatile unsigned long dma_sdar; /* SDMA address reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
729 volatile unsigned char dma_sdsr; /* SDMA status reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
730 volatile unsigned char RSRVD12[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
731 volatile unsigned char dma_sdmr; /* SDMA mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
732 volatile unsigned char RSRVD13[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
733 volatile unsigned char dma_idsr1; /* IDMA1 status reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
734 volatile unsigned char RSRVD14[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
735 volatile unsigned char dma_idmr1; /* IDMA1 mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
736 volatile unsigned char RSRVD15[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
737 volatile unsigned char dma_idsr2; /* IDMA2 status reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
738 volatile unsigned char RSRVD16[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
739 volatile unsigned char dma_idmr2; /* IDMA2 mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
740 volatile unsigned char RSRVD17[0x13];
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jlarmour
parents:
diff changeset
741
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jlarmour
parents:
diff changeset
742 /* CPM Interrupt Controller */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
743 volatile unsigned short cpmi_civr; /* CP interrupt vector reg */
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jlarmour
parents:
diff changeset
744 volatile unsigned char RSRVD19[0xe];
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jlarmour
parents:
diff changeset
745 volatile unsigned long cpmi_cicr; /* CP interrupt configuration reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
746 volatile unsigned long cpmi_cipr; /* CP interrupt pending reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
747 volatile unsigned long cpmi_cimr; /* CP interrupt mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
748 volatile unsigned long cpmi_cisr; /* CP interrupt in-service reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
749
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
750 /* I/O port */
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jlarmour
parents:
diff changeset
751 volatile unsigned short pio_padir; /* port A data direction reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
752 volatile unsigned short pio_papar; /* port A pin assignment reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
753 volatile unsigned short pio_paodr; /* port A open drain reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
754 volatile unsigned short pio_padat; /* port A data register */
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jlarmour
parents:
diff changeset
755 volatile unsigned char RSRVD20[0x8];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
756 volatile unsigned short pio_pcdir; /* port C data direction reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
757 volatile unsigned short pio_pcpar; /* port C pin assignment reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
758 volatile unsigned short pio_pcso; /* port C special options */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
759 volatile unsigned short pio_pcdat; /* port C data register */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
760 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
761 unsigned char RSRVD64[6];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
762 volatile unsigned short pio_pddir; /* port D Data Direction reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
763 volatile unsigned short pio_pdpar; /* port D pin assignment reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
764 unsigned char RSRVD65[2];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
765 volatile unsigned short pio_pddat; /* port D data reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
766 volatile unsigned char RSRVD21[0x8];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
767
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
768 /* CPM Timer */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
769 volatile unsigned short timer_tgcr; /* timer global configuration reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
770 volatile unsigned char RSRVD22[0xe];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
771 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
772 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
773 volatile unsigned short timer_trr1; /* timer 1 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
774 volatile unsigned short timer_trr2; /* timer 2 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
775 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
776 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
777 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
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jlarmour
parents:
diff changeset
778 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
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jlarmour
parents:
diff changeset
779 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
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jlarmour
parents:
diff changeset
780 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
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jlarmour
parents:
diff changeset
781 volatile unsigned short timer_trr3; /* timer 3 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
782 volatile unsigned short timer_trr4; /* timer 4 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
783 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
784 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
785 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
786 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
787 volatile unsigned short timer_ter1; /* timer 1 event reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
788 volatile unsigned short timer_ter2; /* timer 2 event reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
789 volatile unsigned short timer_ter3; /* timer 3 event reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
790 volatile unsigned short timer_ter4; /* timer 4 event reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
791 volatile unsigned char RSRVD23[0x8];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
792
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
793 /* CP */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
794 volatile unsigned short cp_cr; /* command register */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
795 volatile unsigned char RSRVD24[0x2];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
796 volatile unsigned short cp_rccr; /* main configuration reg */
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jlarmour
parents:
diff changeset
797 volatile unsigned char RSRVD25;
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
798 volatile unsigned char cp_resv1; /* RSRVD reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
799 volatile unsigned long cp_resv2; /* RSRVD reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
800 volatile unsigned short cp_rctr1; /* ram break register 1 */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
801 volatile unsigned short cp_rctr2; /* ram break register 2 */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
802 volatile unsigned short cp_rctr3; /* ram break register 3 */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
803 volatile unsigned short cp_rctr4; /* ram break register 4 */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
804 volatile unsigned char RSRVD26[0x2];
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jlarmour
parents:
diff changeset
805 volatile unsigned short cp_rter; /* RISC timers event reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
806 volatile unsigned char RSRVD27[0x2];
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jlarmour
parents:
diff changeset
807 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
808 volatile unsigned char RSRVD28[0x14];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
809
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jlarmour
parents:
diff changeset
810 /* BRG */
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jlarmour
parents:
diff changeset
811 volatile unsigned long brgc1; /* BRG1 configuration reg */
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jlarmour
parents:
diff changeset
812 volatile unsigned long brgc2; /* BRG2 configuration reg */
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jlarmour
parents:
diff changeset
813 volatile unsigned long brgc3; /* BRG3 configuration reg */
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jlarmour
parents:
diff changeset
814 volatile unsigned long brgc4; /* BRG4 configuration reg */
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jlarmour
parents:
diff changeset
815
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jlarmour
parents:
diff changeset
816 /* SCC registers */
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jlarmour
parents:
diff changeset
817 struct scc_regs {
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jlarmour
parents:
diff changeset
818 volatile unsigned long scc_gsmr_l; /* SCC Gen mode (LOW) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
819 volatile unsigned long scc_gsmr_h; /* SCC Gen mode (HIGH) */
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jlarmour
parents:
diff changeset
820 volatile unsigned short scc_psmr; /* protocol specific mode register */
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jlarmour
parents:
diff changeset
821 volatile unsigned char RSRVD29[0x2];
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jlarmour
parents:
diff changeset
822 volatile unsigned short scc_todr; /* SCC transmit on demand */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
823 volatile unsigned short scc_dsr; /* SCC data sync reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
824 volatile unsigned short scc_scce; /* SCC event reg */
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jlarmour
parents:
diff changeset
825 volatile unsigned char RSRVD30[0x2];
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jlarmour
parents:
diff changeset
826 volatile unsigned short scc_sccm; /* SCC mask reg */
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jlarmour
parents:
diff changeset
827 volatile unsigned char RSRVD31[0x1];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
828 volatile unsigned char scc_sccs; /* SCC status reg */
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jlarmour
parents:
diff changeset
829 volatile unsigned char RSRVD32[0x8];
175
e7780801e1a7 Merge from eCos master repository on 2001-07-31-19:15:01-BST
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parents: 147
diff changeset
830 } scc_regs[4];
32
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jlarmour
parents:
diff changeset
831
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jlarmour
parents:
diff changeset
832 /* SMC */
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jlarmour
parents:
diff changeset
833 struct smc_regs {
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jlarmour
parents:
diff changeset
834 volatile unsigned char RSRVD34[0x2];
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jlarmour
parents:
diff changeset
835 volatile unsigned short smc_smcmr; /* SMC mode reg */
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jlarmour
parents:
diff changeset
836 volatile unsigned char RSRVD35[0x2];
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jlarmour
parents:
diff changeset
837 volatile unsigned char smc_smce; /* SMC event reg */
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jlarmour
parents:
diff changeset
838 volatile unsigned char RSRVD36[0x3];
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jlarmour
parents:
diff changeset
839 volatile unsigned char smc_smcm; /* SMC mask reg */
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jlarmour
parents:
diff changeset
840 volatile unsigned char RSRVD37[0x5];
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jlarmour
parents:
diff changeset
841 } smc_regs[2];
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jlarmour
parents:
diff changeset
842
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jlarmour
parents:
diff changeset
843 /* SPI */
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jlarmour
parents:
diff changeset
844 volatile unsigned short spi_spmode; /* SPI mode reg */
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jlarmour
parents:
diff changeset
845 volatile unsigned char RSRVD38[0x4];
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jlarmour
parents:
diff changeset
846 volatile unsigned char spi_spie; /* SPI event reg */
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jlarmour
parents:
diff changeset
847 volatile unsigned char RSRVD39[0x3];
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jlarmour
parents:
diff changeset
848 volatile unsigned char spi_spim; /* SPI mask reg */
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parents:
diff changeset
849 volatile unsigned char RSRVD40[0x2];
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jlarmour
parents:
diff changeset
850 volatile unsigned char spi_spcom; /* SPI command reg */
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parents:
diff changeset
851 volatile unsigned char RSRVD41[0x4];
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parents:
diff changeset
852
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parents:
diff changeset
853 /* PIP */
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jlarmour
parents:
diff changeset
854 volatile unsigned short pip_pipc; /* pip configuration reg */
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jlarmour
parents:
diff changeset
855 volatile unsigned char RSRVD42[0x2];
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jlarmour
parents:
diff changeset
856 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
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jlarmour
parents:
diff changeset
857 volatile unsigned long pip_pbdir; /* port b data direction reg */
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parents:
diff changeset
858 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
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jlarmour
parents:
diff changeset
859 volatile unsigned char RSRVD43[0x2];
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jlarmour
parents:
diff changeset
860 volatile unsigned short pip_pbodr; /* port b open drain reg */
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jlarmour
parents:
diff changeset
861 volatile unsigned long pip_pbdat; /* port b data reg */
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jlarmour
parents:
diff changeset
862 volatile unsigned char RSRVD44[0x18];
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jlarmour
parents:
diff changeset
863
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jlarmour
parents:
diff changeset
864 /* Serial Interface */
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jlarmour
parents:
diff changeset
865 volatile unsigned long si_simode; /* SI mode register */
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jlarmour
parents:
diff changeset
866 volatile unsigned char si_sigmr; /* SI global mode register */
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jlarmour
parents:
diff changeset
867 volatile unsigned char RSRVD45;
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jlarmour
parents:
diff changeset
868 volatile unsigned char si_sistr; /* SI status register */
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jlarmour
parents:
diff changeset
869 volatile unsigned char si_sicmr; /* SI command register */
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jlarmour
parents:
diff changeset
870 volatile unsigned char RSRVD46[0x4];
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jlarmour
parents:
diff changeset
871 volatile unsigned long si_sicr; /* SI clock routing */
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jlarmour
parents:
diff changeset
872 volatile unsigned long si_sirp; /* SI ram pointers */
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jlarmour
parents:
diff changeset
873 volatile unsigned char RSRVD47[0x10c];
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jlarmour
parents:
diff changeset
874 volatile unsigned char si_siram[0x200];/* SI routing ram */
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parents:
diff changeset
875 volatile unsigned short lcd_lcolr[256]; /* LCD Color RAM -- REV A.x */
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jlarmour
parents:
diff changeset
876 volatile unsigned char RSRVD48[0x1000];
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jlarmour
parents:
diff changeset
877
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jlarmour
parents:
diff changeset
878 /* BASE + 0x2000: user data memory */
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
879 volatile unsigned char udata_ucode[0x800]; /* user data bd's Ucode*/
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
880 volatile unsigned char bd[0x700]; /* buffer descriptors, data */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
881 volatile unsigned char udata_ext[0x100]; /* extension area for downloaded ucode */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
882 volatile unsigned char RSRVD49[0x0C00];
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jlarmour
parents: 66
diff changeset
883
32
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jlarmour
parents:
diff changeset
884 /* BASE + 0x3c00: PARAMETER RAM */
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jlarmour
parents:
diff changeset
885 union {
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jlarmour
parents:
diff changeset
886 struct scc_pram {
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jlarmour
parents:
diff changeset
887 union {
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jlarmour
parents:
diff changeset
888 struct hdlc_pram h;
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jlarmour
parents:
diff changeset
889 struct uart_pram u;
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jlarmour
parents:
diff changeset
890 struct bisync_pram b;
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jlarmour
parents:
diff changeset
891 struct transparent_pram t;
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jlarmour
parents:
diff changeset
892 struct async_hdlc_pram a;
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jlarmour
parents:
diff changeset
893 unsigned char RSRVD50[0x80];
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jlarmour
parents:
diff changeset
894 } pscc; /* scc parameter area (protocol dependent) */
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jlarmour
parents:
diff changeset
895
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jlarmour
parents:
diff changeset
896 union {
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jlarmour
parents:
diff changeset
897 struct {
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jlarmour
parents:
diff changeset
898 struct i2c_pram i2c;
147
d397fc472bcf Merge from eCos master repository on 2001-01-05-06:43:02-GMT
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diff changeset
899 unsigned char RSRVD56[0x10];
32
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parents:
diff changeset
900 struct idma_pram idma1;
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jlarmour
parents:
diff changeset
901 } i2c_idma;
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jlarmour
parents:
diff changeset
902 struct {
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parents:
diff changeset
903 struct spi_pram spi;
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jlarmour
parents:
diff changeset
904 struct timer_pram timer;
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jlarmour
parents:
diff changeset
905 struct idma_pram idma2;
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parents:
diff changeset
906 } spi_timer_idma;
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parents:
diff changeset
907 struct {
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parents:
diff changeset
908 union {
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parents:
diff changeset
909 struct smc_uart_pram u;
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jlarmour
parents:
diff changeset
910 struct smc_trnsp_pram t;
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parents:
diff changeset
911 struct centronics_pram c;
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parents:
diff changeset
912 } psmc;
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parents:
diff changeset
913 unsigned char modem_param[0x40];
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parents:
diff changeset
914 } smc_modem;
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parents:
diff changeset
915 struct {
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parents:
diff changeset
916 unsigned char RSRVD54[0x40];
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parents:
diff changeset
917 struct ucode_pram ucode;
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parents:
diff changeset
918 } pucode;
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parents:
diff changeset
919 } pothers;
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parents:
diff changeset
920 } scc;
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parents:
diff changeset
921 struct ethernet_pram enet_scc;
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jlarmour
parents:
diff changeset
922 unsigned char pr[0x100];
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parents:
diff changeset
923 } pram[4];
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parents:
diff changeset
924 } EPPC;
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parents:
diff changeset
925
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parents:
diff changeset
926
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parents:
diff changeset
927 static inline EPPC *eppc_base(void)
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parents:
diff changeset
928 {
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parents:
diff changeset
929 EPPC *retval;
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parents:
diff changeset
930
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parents:
diff changeset
931 asm volatile (
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jlarmour
parents:
diff changeset
932 "mfspr %0,638 \n\t"
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jlarmour
parents:
diff changeset
933 "andis. %0,%0,65535 \n\t"
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parents:
diff changeset
934 : "=r" (retval)
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parents:
diff changeset
935 : /* no inputs */ );
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parents:
diff changeset
936
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parents:
diff changeset
937 return retval;
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parents:
diff changeset
938 }
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jlarmour
parents:
diff changeset
939
860
8e23fe1ac05e Improve processor type support. Add baud rate generator allocation.
gthomas
parents: 812
diff changeset
940 // Function used to reset [only once!] the CPM
8e23fe1ac05e Improve processor type support. Add baud rate generator allocation.
gthomas
parents: 812
diff changeset
941 __externC void _mpc8xx_reset_cpm(void);
32
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parents:
diff changeset
942
435
a6484a9a16c6 Improve generalized support for MPC/QUICC based platforms
gthomas
parents: 363
diff changeset
943 // Function used to allocate space in shared memory area
a6484a9a16c6 Improve generalized support for MPC/QUICC based platforms
gthomas
parents: 363
diff changeset
944 // typically used for buffer descriptors, etc.
804
c309f36b6de9 Better CPM/DPRAM handling. Fix minor bug in hal_diag_putc().
gthomas
parents: 435
diff changeset
945 __externC unsigned short _mpc8xx_allocBd(int len);
435
a6484a9a16c6 Improve generalized support for MPC/QUICC based platforms
gthomas
parents: 363
diff changeset
946
860
8e23fe1ac05e Improve processor type support. Add baud rate generator allocation.
gthomas
parents: 812
diff changeset
947 // Function used to manage the pool of baud rate generators
8e23fe1ac05e Improve processor type support. Add baud rate generator allocation.
gthomas
parents: 812
diff changeset
948 __externC unsigned long *_mpc8xx_allocate_brg(int port);
8e23fe1ac05e Improve processor type support. Add baud rate generator allocation.
gthomas
parents: 812
diff changeset
949
435
a6484a9a16c6 Improve generalized support for MPC/QUICC based platforms
gthomas
parents: 363
diff changeset
950 #define QUICC_BD_BASE 0x2000 // Start of shared memory
812
515a36c8eb9d Improve handling of CPM/DPRAM aloocation.
gthomas
parents: 804
diff changeset
951 #define QUICC_BD_END 0x3000 // End of shared memory
435
a6484a9a16c6 Improve generalized support for MPC/QUICC based platforms
gthomas
parents: 363
diff changeset
952
32
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parents:
diff changeset
953
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parents:
diff changeset
954 #endif /* __ASSEMBLER__ */
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parents:
diff changeset
955
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jlarmour
parents:
diff changeset
956 /* Memory Periodic Timer Prescaler Register values */
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jlarmour
parents:
diff changeset
957 #define PTP_DIV2 0x2000
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parents:
diff changeset
958 #define PTP_DIV4 0x1000
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parents:
diff changeset
959 #define PTP_DIV8 0x0800
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parents:
diff changeset
960 #define PTP_DIV16 0x0400
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parents:
diff changeset
961 #define PTP_DIV32 0x0200
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parents:
diff changeset
962 #define PTP_DIV64 0x0100
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parents:
diff changeset
963
76
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jlarmour
parents: 66
diff changeset
964 // Command Processor Module (CPM)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
965
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jlarmour
parents: 66
diff changeset
966 // Buffer descriptor control bits
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
967 #define QUICC_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
968 #define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list
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jlarmour
parents: 66
diff changeset
969 #define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
970 #define QUICC_BD_CTL_Last 0x0800 // Last buffer in a sequence
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jlarmour
parents: 66
diff changeset
971 #define QUICC_BD_CTL_MASK 0xB000 // User settable bits
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
972
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
973 // Command register
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jlarmour
parents: 66
diff changeset
974 #define QUICC_CPM_CR_INIT_TXRX 0x0000 // Initialize both Tx and Rx chains
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jlarmour
parents: 66
diff changeset
975 #define QUICC_CPM_CR_INIT_RX 0x0100 // Initialize Rx chains
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jlarmour
parents: 66
diff changeset
976 #define QUICC_CPM_CR_INIT_TX 0x0200 // Initialize Tx chains
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jlarmour
parents: 66
diff changeset
977 #define QUICC_CPM_CR_HUNT_MODE 0x0300 // Start "hunt" mode
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jlarmour
parents: 66
diff changeset
978 #define QUICC_CPM_CR_STOP_TX 0x0400 // Stop transmitter
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jlarmour
parents: 66
diff changeset
979 #define QUICC_CPM_CR_RESTART_TX 0x0600 // Restart transmitter
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
980 #define QUICC_CPM_CR_RESET 0x8000 // Reset CPM
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
981 #define QUICC_CPM_CR_BUSY 0x0001 // Kick CPM - busy indicator
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
982
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
983 // CPM channels
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
984 #define QUICC_CPM_SCC1 0x0000
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
985 #define QUICC_CPM_I2C 0x0010
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents: 66
diff changeset
986 #define QUICC_CPM_SCC2 0x0040
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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987 #define QUICC_CPM_SCC3 0x0080
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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988 #define QUICC_CPM_SMC1 0x0090
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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989 #define QUICC_CPM_SCC4 0x00C0
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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990 #define QUICC_CPM_SMC2 0x00D0
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991
860
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992 // SMC Events (interrupts)
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993 #define QUICC_SMCE_BRK 0x10 // Break received
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994 #define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
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995 #define QUICC_SMCE_TX 0x02 // Tx interrupt
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996 #define QUICC_SMCE_RX 0x01 // Rx interrupt
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997
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998 // SMC Mode Register
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999 #define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length
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1000 #define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
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1001 #define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
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1002 #define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
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1003 #define QUICC_SMCMR_UART (2<<4) // UART mode
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1004 #define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
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1005 #define QUICC_SMCMR_REN (1<<0) // Enable receiver
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1006
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1007 // SMC Commands
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1008 #define QUICC_SMC_CMD_InitTxRx (0<<8)
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1009 #define QUICC_SMC_CMD_InitTx (1<<8)
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1010 #define QUICC_SMC_CMD_InitRx (2<<8)
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1011 #define QUICC_SMC_CMD_StopTx (4<<8)
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1012 #define QUICC_SMC_CMD_RestartTx (6<<8)
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1013 #define QUICC_SMC_CMD_Reset 0x8000
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1014 #define QUICC_SMC_CMD_Go 0x0001
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1015
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1016 // SCC PSMR masks ....
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1017 #define QUICC_SCC_PSMR_ASYNC 0x8000
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1018 #define QUICC_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb)
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1019 #define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8)
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1020 #define QUICC_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled)
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1021 #define QUICC_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high)
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1022 #define QUICC_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high)
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1023
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1024 // SCC DSR masks
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1025 #define QUICC_SCC_DSR_FULL 0x7e7e
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1026 #define QUICC_SCC_DSR_HALF 0x467e
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1027
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1028 // SCC GSMR masks ...
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1029 #define QUICC_SCC_GSMR_H_INIT 0x00000060
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1030 #define QUICC_SCC_GSMR_L_INIT 0x00028004
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1031 #define QUICC_SCC_GSMR_L_Tx 0x00000010
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1032 #define QUICC_SCC_GSMR_L_Rx 0x00000020
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1033
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1034 // SCC Events (interrupts)
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1035 #define QUICC_SCCE_BRK 0x0040
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1036 #define QUICC_SCCE_BSY 0x0004
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1037 #define QUICC_SCCE_TX 0x0002
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1038 #define QUICC_SCCE_RX 0x0001
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1039
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1040 #endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H