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changeset 804:c309f36b6de9

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Better CPM/DPRAM handling. Fix minor bug in hal_diag_putc().
author gthomas
date Wed, 05 Mar 2003 17:15:43 +0000
parents 4ce5ea5be254
children 422f7c9c87d9
files packages/hal/powerpc/mpc8xx/current/ChangeLog packages/hal/powerpc/mpc8xx/current/src/var_misc.c packages/hal/powerpc/quicc/current/ChangeLog packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl packages/hal/powerpc/quicc/current/include/ppc8xx.h packages/hal/powerpc/quicc/current/src/cpm.c packages/hal/powerpc/quicc/current/src/quicc_smc1.c packages/hal/powerpc/viper/current/src/viper.S
diffstat 8 files changed, 147 insertions(+), 52 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/powerpc/mpc8xx/current/ChangeLog
+++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog
@@ -1,3 +1,7 @@
+2003-03-05  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/var_misc.c (hal_variant_init): Reset CPM (ROM/monitor only).
+
 2003-03-05  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* include/variant.inc: Don't let FP be set in MSR in common HAL.
--- a/packages/hal/powerpc/mpc8xx/current/src/var_misc.c
+++ b/packages/hal/powerpc/mpc8xx/current/src/var_misc.c
@@ -72,6 +72,10 @@ hal_variant_init(void)
         ictrl |= ICTRL_NOSERSHOW;
         CYGARC_MTSPR (ICTRL, ictrl);
     }
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
+    // Reset CPM
+    _mpc8xx_reset_cpm();
+#endif
 }
 
 //--------------------------------------------------------------------------
--- a/packages/hal/powerpc/quicc/current/ChangeLog
+++ b/packages/hal/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,14 @@
+2003-03-05  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/quicc_smc1.c: Need to flush data cache because the serial
+	driver may set use buffers in cacheable memory.  Without this,
+	diag_printf() falls over if the serial driver is ever used.
+
+	* src/cpm.c: New file with CPM/DPRAM support.
+
+	* include/ppc8xx.h: 
+	* cdl/hal_powerpc_quicc.cdl: Split out support for CPM/DPRAM.
+
 2002-11-26  Gary Thomas  <gthomas@ecoscentric.com>
 
 	* src/quicc_smc1.c: Initialize BD allocation point.  Note that it is
--- a/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
+++ b/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
@@ -9,7 +9,7 @@
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
@@ -100,7 +100,7 @@ cdl_package CYGPKG_HAL_QUICC {
           Port SCC3 is available for serial I/O"
     }
 
-    compile       quicc_smc1.c
+    compile       quicc_smc1.c cpm.c
 
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
        display      "Number of communication channels on the board"
--- a/packages/hal/powerpc/quicc/current/include/ppc8xx.h
+++ b/packages/hal/powerpc/quicc/current/include/ppc8xx.h
@@ -12,7 +12,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -939,7 +939,8 @@ static inline EPPC *eppc_base(void)
 
 // Function used to allocate space in shared memory area
 // typically used for buffer descriptors, etc.
-__externC unsigned short cyg_hal_allocBd(int len);
+__externC void _mpc8xx_reset_cpm(void);
+__externC unsigned short _mpc8xx_allocBd(int len);
 
 #define QUICC_BD_BASE               0x2000  // Start of shared memory
 
new file mode 100644
--- /dev/null
+++ b/packages/hal/powerpc/quicc/current/src/cpm.c
@@ -0,0 +1,107 @@
+//==========================================================================
+//
+//      cpm.c
+//
+//      PowerPC QUICC support functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Gary Thomas 
+// Contributors: 
+// Date:         2003-03-04
+// Purpose:      Common support for the QUICC/CPM
+// Description:  
+//               
+// Usage:
+// Notes:        
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_powerpc_quicc.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+
+#ifdef CYGPKG_HAL_POWERPC_MPC860
+// eCos headers decribing PowerQUICC:
+#include <cyg/hal/quicc/ppc8xx.h>
+
+// Information about DPRAM usage
+// This lets the CPM/DPRAM information be shared by all environments
+//
+static short *nextBd = (short *)(CYGHWR_HAL_VSR_TABLE + 0x1F0);
+
+/*
+ * Reset the communications processor
+ */
+
+void
+_mpc8xx_reset_cpm(void)
+{
+    EPPC *eppc = eppc_base();
+    int i;
+    static int init_done = 0;
+
+    if (init_done) return;
+    init_done++;
+
+    eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
+    memset(eppc->pram, 0, 0x400);
+    for (i = 0; i < 100000; i++);
+
+    *nextBd = QUICC_BD_BASE;
+}
+
+//
+// Allocate a chunk of memory in the shared CPM memory, typically
+// used for buffer descriptors, etc.  The length will be aligned
+// to a multiple of 8 bytes.
+//
+unsigned short
+_mpc8xx_allocBd(int len)
+{
+    unsigned short bd = *nextBd;
+
+    len = (len + 7) & ~7;  // Multiple of 8 bytes
+    *nextBd += len;
+    return bd;
+}
+
+#endif // CYGPKG_HAL_POWERPC_MPC860
+// EOF cpm.c
--- a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
+++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
@@ -9,7 +9,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -133,45 +133,6 @@ static struct port_info ports[] = {
 #define QUICC_SMCE_RX  0x01  // Rx interrupt
 
 /*
- * Reset the communications processor
- */
-
-static short nextBd = QUICC_BD_BASE + 0x400;
-
-static void
-reset_cpm(void)
-{
-    EPPC *eppc = eppc_base();
-    int i;
-    static int init_done = 0;
-
-    if (init_done) return;
-    init_done++;
-
-    eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
-    memset(eppc->pram, 0, 0x400);
-    for (i = 0; i < 100000; i++);
-
-    nextBd = QUICC_BD_BASE;
-
-}
-
-//
-// Allocate a chunk of memory in the shared CPM memory, typically
-// used for buffer descriptors, etc.  The length will be aligned
-// to a multiple of 8 bytes.
-//
-unsigned short
-cyg_hal_allocBd(int len)
-{
-    unsigned short bd = nextBd;
-
-    len = (len + 7) & ~7;  // Multiple of 8 bytes
-    nextBd += len;
-    return bd;
-}
-
-/*
  *  Initialize SMCX as a uart.
  *
  *  Comments below reference Motorola's "MPC860 User Manual".
@@ -190,7 +151,7 @@ cyg_hal_smcx_init_channel(struct port_in
     if (info->init) return;
     info->init = 1;
 
-    reset_cpm();
+    _mpc8xx_reset_cpm();
 
     switch (port) {
 #if CYGNUM_HAL_QUICC_SMC1 > 0
@@ -240,8 +201,8 @@ cyg_hal_smcx_init_channel(struct port_in
      *  Set pointers to buffer descriptors.
      *  (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
      */
-    uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
-    uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+    uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+    uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
 
     /*
      *  SDMA & LCD bus request level 5
@@ -335,6 +296,7 @@ cyg_hal_smcx_putc(void* __ch_data, cyg_u
     volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
     volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
     int timeout;
+    int cache_state;
     CYGARC_HAL_SAVE_GP();
 
     /* tx buffer descriptor */
@@ -358,8 +320,14 @@ cyg_hal_smcx_putc(void* __ch_data, cyg_u
         bd->length = 0;
     }
 
-    bd->buffer[bd->length++] = ch;
+    bd->length = 1;
+    bd->buffer[0] = ch;
     bd->ctrl      |= QUICC_BD_CTL_Ready;
+    // Flush cache if necessary - buffer may be in cacheable memory
+    HAL_DCACHE_IS_ENABLED(cache_state);
+    if (cache_state) {
+      HAL_DCACHE_FLUSH(bd->buffer, 1);
+    }
 
 #ifdef CYGDBG_DIAG_BUF
         enable_diag_uart = 0;
@@ -619,7 +587,7 @@ cyg_hal_sccx_init_channel(struct port_in
     if (info->init) return;
     info->init = 1;
 
-    reset_cpm();
+    _mpc8xx_reset_cpm();
 
     /*
      *  Set up the Port pins for UART operation.
@@ -706,8 +674,8 @@ cyg_hal_sccx_init_channel(struct port_in
      *  Set pointers to buffer descriptors.
      */
     memset((void *)uart_pram, 0xFF, 0x100);
-    uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
-    uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+    uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+    uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
 
     /*
      *  SDMA & LCD bus request level 5
--- a/packages/hal/powerpc/viper/current/src/viper.S
+++ b/packages/hal/powerpc/viper/current/src/viper.S
@@ -364,7 +364,7 @@ 10:
 	 */
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED > 63)
 	lwi	r3,0x00420000  // Bus divide by 2
-#else        
+#else
 	lwi	r3,0x00400000
 #endif        
 	stw	r3,SCCR(r4)