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annotate packages/hal/sh/arch/current/include/hal_intr.h @ 1777:c16341b1bac6 default tip

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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents d2c90368aeef
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1 #ifndef CYGONCE_HAL_INTR_H
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2 #define CYGONCE_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //==========================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): jskov
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47 // Contributors: jskov,
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48 // Date: 1999-04-24
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49 // Purpose: Define Interrupt support
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // interrupts and the clock.
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52 //
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53 // Usage:
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54 // #include <cyg/hal/hal_intr.h>
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55 // ...
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56 //
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57 //
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58 //####DESCRIPTIONEND####
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59 //
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60 //==========================================================================
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61
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62 #include <pkgconf/hal.h>
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63
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64 #include <cyg/hal/var_intr.h>
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66 // More include statements below. First part of this file must be
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67 // usable for both assembly and C files, so only use defines here.
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68
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69 #include CYGBLD_HAL_VAR_INTR_MODEL_H
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71 #ifndef __ASSEMBLER__
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72
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73 #include <cyg/infra/cyg_type.h>
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74
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75 #include <cyg/hal/sh_regs.h> // register definitions
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76 #include <cyg/hal/hal_io.h> // io macros
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77 #include <cyg/infra/cyg_ass.h> // CYG_FAIL
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78
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79 //--------------------------------------------------------------------------
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80 // Static data used by HAL
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81
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82 // ISR tables
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83 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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84 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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85 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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86 // VSR table
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87 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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88
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89 //--------------------------------------------------------------------------
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90 // Default ISR
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91 // The #define is used to test whether this routine exists, and to allow
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92 // us to call it.
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93
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94 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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95
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96 #define HAL_DEFAULT_ISR hal_default_isr
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97
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98 //--------------------------------------------------------------------------
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99 // Interrupt state storage
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100
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101 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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102
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103 //--------------------------------------------------------------------------
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104 // Interrupt control macros
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105 //
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106 // Note that these macros control interrupt state by setting the Imask
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107 // of the SR rather than the (more obvious) BL. This is because a CPU
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108 // reset is forced if execptions (such as breakpoints) are generated
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109 // while the BL flag is set.
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110
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111 #define HAL_DISABLE_INTERRUPTS(_old_) \
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112 CYG_MACRO_START \
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113 cyg_uint32 _tmp_; \
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114 asm volatile ( \
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115 "stc sr,%1 \n\t" \
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116 "mov %2,%0 \n\t" \
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117 "and %1,%0 \n\t" \
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118 "or %2,%1 \n\t" \
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119 "ldc %1,sr \n\t" \
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120 : "=&r"(_old_), "=&r" (_tmp_) \
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121 : "r" (CYGARC_REG_SR_IMASK) \
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122 ); \
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123 CYG_MACRO_END
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124
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125 #define HAL_ENABLE_INTERRUPTS() \
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126 CYG_MACRO_START \
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127 cyg_uint32 _tmp_; \
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128 asm volatile ( \
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129 "stc sr,%0 \n\t" \
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130 "and %1,%0 \n\t" \
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131 "ldc %0,sr \n\t" \
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132 : "=&r" (_tmp_) \
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133 : "r" (~CYGARC_REG_SR_IMASK) \
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134 ); \
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135 CYG_MACRO_END
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136
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137 #define HAL_RESTORE_INTERRUPTS(_old_) \
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138 CYG_MACRO_START \
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139 cyg_uint32 _tmp1_, _tmp2_; \
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140 asm volatile ( \
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141 "stc sr,%0 \n\t" \
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142 "and %3,%0 \n\t" \
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143 "not %3,%1 \n\t" \
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144 "and %2,%1 \n\t" \
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145 "or %1,%0 \n\t" \
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146 "ldc %0,sr \n\t" \
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147 : "=&r" (_tmp1_), "=&r" (_tmp2_) \
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148 : "r" (_old_), "r" (~CYGARC_REG_SR_IMASK) \
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149 ); \
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150 CYG_MACRO_END
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151
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152 #define HAL_QUERY_INTERRUPTS(_old_) \
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153 CYG_MACRO_START \
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154 asm volatile ( \
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155 "stc sr,%0 \n\t" \
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156 "and %1,%0 \n\t" \
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157 : "=&r"(_old_) \
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158 : "r" (CYGARC_REG_SR_IMASK) \
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159 ); \
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160 CYG_MACRO_END
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161
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162 //--------------------------------------------------------------------------
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163 // Vector translation.
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164
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165 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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166
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167 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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168
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169 #else
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170
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171 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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172
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173 #endif
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174
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175 //--------------------------------------------------------------------------
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176 // Routine to execute DSRs using separate interrupt stack
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177
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178 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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179
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180 externC void hal_interrupt_stack_call_pending_DSRs(void);
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181 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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182 hal_interrupt_stack_call_pending_DSRs()
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183
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184 // these are offered solely for stack usage testing
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185 // if they are not defined, then there is no interrupt stack.
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186 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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187 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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188 // use them to declare these extern however you want:
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189 // extern char HAL_INTERRUPT_STACK_BASE[];
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190 // extern char HAL_INTERRUPT_STACK_TOP[];
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191 // is recommended
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192 #endif
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193
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194 //--------------------------------------------------------------------------
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195 // Interrupt and VSR attachment macros
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196
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197 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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198 CYG_MACRO_START \
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199 cyg_uint32 _index_; \
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200 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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201 \
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202 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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203 (_state_) = 0; \
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204 else \
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205 (_state_) = 1; \
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206 CYG_MACRO_END
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207
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208 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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209 CYG_MACRO_START \
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210 cyg_uint32 _index_; \
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211 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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212 \
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213 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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214 { \
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215 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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216 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
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217 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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218 } \
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219 CYG_MACRO_END
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220
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221 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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222 CYG_MACRO_START \
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223 cyg_uint32 _index_; \
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224 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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225 \
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226 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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227 { \
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228 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
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229 hal_interrupt_data[_index_] = 0; \
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230 hal_interrupt_objects[_index_] = 0; \
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231 } \
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232 CYG_MACRO_END
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233
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234 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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235 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
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236
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237
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238 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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239 CYG_MACRO_START \
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240 if( _poldvsr_ != NULL ) \
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241 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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242 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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243 CYG_MACRO_END
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244
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245 // This is an ugly name, but what it means is: grab the VSR back to eCos
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246 // internal handling, or if you like, the default handler. But if
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247 // cooperating with GDB and CygMon, the default behaviour is to pass most
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248 // exceptions to CygMon. This macro undoes that so that eCos handles the
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249 // exception. So use it with care.
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250
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251 externC void cyg_hal_default_interrupt_vsr( void );
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252 externC void cyg_hal_default_exception_vsr( void );
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253 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
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254 CYG_MACRO_START \
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255 if( (void*)_poldvsr_ != (void*)NULL ) \
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256 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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257 hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
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258 ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
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259 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
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260 CYG_MACRO_END
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261
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262
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263 //--------------------------------------------------------------------------
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264 // Interrupt controller(s) access
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265 //
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266
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267 externC void hal_interrupt_set_level(int, int);
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268 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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269 hal_interrupt_set_level(_vector_, _level_);
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270
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271 externC void hal_interrupt_mask(int);
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272 #define HAL_INTERRUPT_MASK( _vector_ ) \
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273 hal_interrupt_mask(_vector_);
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274
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275 externC void hal_interrupt_unmask(int);
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276 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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277 hal_interrupt_unmask(_vector_);
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278
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279 externC void hal_interrupt_acknowledge(int);
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280 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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281 hal_interrupt_acknowledge(_vector_);
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282
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283 externC void hal_interrupt_configure(int, int, int);
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284 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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285 hal_interrupt_configure(_vector_, _level_, _up_);
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286
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287 #endif // __ASSEMBLER__
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288
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289 //--------------------------------------------------------------------------
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290 #endif // ifndef CYGONCE_HAL_INTR_H
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291 // End of hal_intr.h