Mercurial > flash_v2

annotate packages/hal/sh/arch/current/include/hal_intr.h @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
parents 2085233a121a
children 489eb5632bc3
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1 #ifndef CYGONCE_HAL_INTR_H
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2 #define CYGONCE_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): jskov
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38 // Contributors: jskov,
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39 // Date: 1999-04-24
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40 // Purpose: Define Interrupt support
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // interrupts and the clock.
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43 //
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44 // Usage:
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45 // #include <cyg/hal/hal_intr.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 #include <pkgconf/hal.h>
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54 #include CYGBLD_HAL_CPU_MODULES_H // INTC module selection
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55
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56 // More include statements below. First part of this file must be
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57 // usable for both assembly and C files, so only use defines here.
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58
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59 //--------------------------------------------------------------------------
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60 // SH3 exception vectors. These correspond to VSRs and are the values
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61 // to use for HAL_VSR_GET/SET
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62 //
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63 // Note that exceptions are decoded - there is a VSR slot for each exception
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64 // source, while interrupts are handled via the same VSR.
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66 #define CYGNUM_HAL_VECTOR_POWERON 0 // power-on
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67 #define CYGNUM_HAL_VECTOR_RESET 1 // reset
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68 #define CYGNUM_HAL_VECTOR_TLBMISS_ACCESS 2 // TLB-miss/invalid load
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69 #define CYGNUM_HAL_VECTOR_TLBMISS_WRITE 3 // TLB-miss/invalid store
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70 #define CYGNUM_HAL_VECTOR_INITIAL_WRITE 4 // initial page write
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71 #define CYGNUM_HAL_VECTOR_TLBERROR_ACCESS 5 // TLB prot violation l
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72 #define CYGNUM_HAL_VECTOR_TLBERROR_WRITE 6 // TLB prot violation s
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73 #define CYGNUM_HAL_VECTOR_DATA_ACCESS 7 // address error (load)
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74 #define CYGNUM_HAL_VECTOR_DATA_WRITE 8 // address error (store)
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75 // define CYGNUM_HAL_VECTOR_RESERVED_9 9
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76 // define CYGNUM_HAL_VECTOR_RESERVED_10 10
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77 #define CYGNUM_HAL_VECTOR_TRAP 11 // unconditional trap
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78 #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 12 // reserved instruction
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79 #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION 13
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80 // illegal instruction in delay slot
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81 // define CYGNUM_HAL_VECTOR_RESERVED_14 14
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82 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 15 // user breakpoint
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83
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84 #define CYG_VECTOR_IS_INTERRUPT(v) \
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85 (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v))
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86
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87 #define CYGNUM_HAL_VECTOR_INTERRUPT 16 // all interrupts
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88
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89 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_POWERON
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90 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTERRUPT
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91 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
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92
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93 #define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1)
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96
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97 // The decoded interrupts.
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98 #define CYGNUM_HAL_INTERRUPT_NMI 0
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99 #define CYGNUM_HAL_INTERRUPT_RESERVED_1E0 1
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100 #define CYGNUM_HAL_INTERRUPT_LVL0 2
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101 #define CYGNUM_HAL_INTERRUPT_LVL1 3
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102 #define CYGNUM_HAL_INTERRUPT_LVL2 4
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103 #define CYGNUM_HAL_INTERRUPT_LVL3 5
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104 #define CYGNUM_HAL_INTERRUPT_LVL4 6
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105 #define CYGNUM_HAL_INTERRUPT_LVL5 7
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106 #define CYGNUM_HAL_INTERRUPT_LVL6 8
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107 #define CYGNUM_HAL_INTERRUPT_LVL7 9
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108 #define CYGNUM_HAL_INTERRUPT_LVL8 10
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109 #define CYGNUM_HAL_INTERRUPT_LVL9 11
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110 #define CYGNUM_HAL_INTERRUPT_LVL10 12
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111 #define CYGNUM_HAL_INTERRUPT_LVL11 13
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112 #define CYGNUM_HAL_INTERRUPT_LVL12 14
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113 #define CYGNUM_HAL_INTERRUPT_LVL13 15
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114 #define CYGNUM_HAL_INTERRUPT_LVL14 16
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115 #define CYGNUM_HAL_INTERRUPT_RESERVED_3E0 17
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116 #define CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 18
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117 #define CYGNUM_HAL_INTERRUPT_TMU1_TUNI1 19
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118 #define CYGNUM_HAL_INTERRUPT_TMU2_TUNI2 20
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119 #define CYGNUM_HAL_INTERRUPT_TMU2_TICPI2 21
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120 #define CYGNUM_HAL_INTERRUPT_RTC_ATI 22
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121 #define CYGNUM_HAL_INTERRUPT_RTC_PRI 23
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122 #define CYGNUM_HAL_INTERRUPT_RTC_CUI 24
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123 #define CYGNUM_HAL_INTERRUPT_SCI_ERI 25
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124 #define CYGNUM_HAL_INTERRUPT_SCI_RXI 26
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125 #define CYGNUM_HAL_INTERRUPT_SCI_TXI 27
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126 #define CYGNUM_HAL_INTERRUPT_SCI_TEI 28
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127 #define CYGNUM_HAL_INTERRUPT_WDT_ITI 29
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128 #define CYGNUM_HAL_INTERRUPT_REF_RCMI 30
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129 #define CYGNUM_HAL_INTERRUPT_REF_ROVI 31
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130
80
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131 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI
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132
76
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133
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134 // CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S.
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135 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI
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136 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 )
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137
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138 // Exception vectors. These are the values used when passed out to an
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139 // external exception handler using cyg_hal_deliver_exception()
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140
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141 // The exception indexes are EXPEVT/0x20
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142
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143 #define CYGNUM_HAL_EXCEPTION_POWERON 0 // power-on
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144 #define CYGNUM_HAL_EXCEPTION_RESET 1 // reset
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145 #define CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS 2 // TLB-miss/invalid load
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146 #define CYGNUM_HAL_EXCEPTION_TLBMISS_WRITE 3 // TLB-miss/invalid store
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147 #define CYGNUM_HAL_EXCEPTION_INITIAL_WRITE 4 // initial page write
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148 #define CYGNUM_HAL_EXCEPTION_TLBERROR_ACCESS 5 // TLB prot violation l
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149 #define CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE 6 // TLB prot violation s
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150 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 7 // address error (load)
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151 #define CYGNUM_HAL_EXCEPTION_DATA_WRITE 8 // address error (store)
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152 // define CYGNUM_HAL_EXCEPTION_RESERVED_9 9
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153 // define CYGNUM_HAL_EXCEPTION_RESERVED_10 10
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154 #define CYGNUM_HAL_EXCEPTION_TRAP 11 // unconditional trap
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155 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 12 // reserved instruction
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156 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION 13
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157 // illegal instruction in delay slot
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158 // define CYGNUM_HAL_EXCEPTION_RESERVED_14 14
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159 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP 15 // user breakpoint
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160
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161 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON
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162 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP
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163 #define CYGNUM_HAL_EXCEPTION_COUNT \
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164 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
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165
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166 // The vector used by the Real time clock
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167 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMU0_TUNI0
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168
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169 #ifndef __ASSEMBLER__
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170
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171 #include <cyg/infra/cyg_type.h>
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172
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173 #include <cyg/hal/sh_regs.h> // register definitions
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174 #include <cyg/hal/hal_io.h> // io macros
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175 #include <cyg/infra/cyg_ass.h> // CYG_FAIL
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176
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177 //--------------------------------------------------------------------------
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178 // Static data used by HAL
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179
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180 // ISR tables
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181 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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182 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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183 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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184 // VSR table
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185 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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186
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187 //--------------------------------------------------------------------------
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188 // Default ISR
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189
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190 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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191
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192 //--------------------------------------------------------------------------
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193 // Interrupt state storage
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194
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195 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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196
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197 //--------------------------------------------------------------------------
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198 // Interrupt control macros
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199 //
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200 // Note that these macros control interrupt state by setting the Imask
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201 // of the SR rather than the (more obvious) BL. This is because a CPU
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202 // reset is forced if execptions (such as breakpoints) are generated
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203 // while the BL flag is set.
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204
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205 #define HAL_DISABLE_INTERRUPTS(_old_) \
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206 CYG_MACRO_START \
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207 cyg_uint32 _tmp_; \
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208 asm volatile ( \
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209 "stc sr,%1 \n\t" \
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210 "mov %2,%0 \n\t" \
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211 "and %1,%0 \n\t" \
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212 "or %2,%1 \n\t" \
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213 "ldc %1,sr \n\t" \
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214 : "=&r"(_old_), "=&r" (_tmp_) \
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215 : "r" (CYGARC_REG_SR_IMASK) \
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216 ); \
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217 CYG_MACRO_END
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218
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219 #define HAL_ENABLE_INTERRUPTS() \
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220 CYG_MACRO_START \
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221 cyg_uint32 _tmp_; \
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222 asm volatile ( \
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223 "stc sr,%0 \n\t" \
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224 "and %1,%0 \n\t" \
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225 "ldc %0,sr \n\t" \
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226 : "=&r" (_tmp_) \
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227 : "r" (~CYGARC_REG_SR_IMASK) \
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228 ); \
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229 CYG_MACRO_END
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230
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231 #define HAL_RESTORE_INTERRUPTS(_old_) \
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232 CYG_MACRO_START \
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233 cyg_uint32 _tmp1_, _tmp2_; \
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234 asm volatile ( \
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235 "stc sr,%0 \n\t" \
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236 "and %3,%0 \n\t" \
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237 "not %3,%1 \n\t" \
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238 "and %2,%1 \n\t" \
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239 "or %1,%0 \n\t" \
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240 "ldc %0,sr \n\t" \
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241 : "=&r" (_tmp1_), "=&r" (_tmp2_) \
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242 : "r" (_old_), "r" (~CYGARC_REG_SR_IMASK) \
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243 ); \
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244 CYG_MACRO_END
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245
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246 #define HAL_QUERY_INTERRUPTS(_old_) \
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247 CYG_MACRO_START \
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248 asm volatile ( \
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249 "stc sr,%0 \n\t" \
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250 "and %1,%0 \n\t" \
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251 : "=&r"(_old_) \
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252 : "r" (CYGARC_REG_SR_IMASK) \
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253 ); \
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254 CYG_MACRO_END
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255
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256 //--------------------------------------------------------------------------
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257 // Vector translation.
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258
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259 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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260
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261 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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262
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263 #else
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264
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265 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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266
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267 #endif
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268
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269 //--------------------------------------------------------------------------
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270 // Routine to execute DSRs using separate interrupt stack
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271
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272 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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273
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274 externC void hal_interrupt_stack_call_pending_DSRs(void);
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275 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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276 hal_interrupt_stack_call_pending_DSRs()
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277
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278 // these are offered solely for stack usage testing
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279 // if they are not defined, then there is no interrupt stack.
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280 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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281 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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282 // use them to declare these extern however you want:
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283 // extern char HAL_INTERRUPT_STACK_BASE[];
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284 // extern char HAL_INTERRUPT_STACK_TOP[];
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285 // is recommended
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286 #endif
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287
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288 //--------------------------------------------------------------------------
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289 // Interrupt and VSR attachment macros
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290
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291 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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292 CYG_MACRO_START \
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293 cyg_uint32 _index_; \
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294 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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295 \
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296 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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297 (_state_) = 0; \
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298 else \
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299 (_state_) = 1; \
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300 CYG_MACRO_END
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301
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302 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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303 CYG_MACRO_START \
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304 cyg_uint32 _index_; \
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305 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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306 \
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307 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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308 { \
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309 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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310 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
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311 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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312 } \
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313 CYG_MACRO_END
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314
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315 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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316 CYG_MACRO_START \
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317 cyg_uint32 _index_; \
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318 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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319 \
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320 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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321 { \
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322 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
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323 hal_interrupt_data[_index_] = 0; \
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324 hal_interrupt_objects[_index_] = 0; \
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325 } \
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326 CYG_MACRO_END
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327
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328 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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329 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
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330
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331
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332 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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333 CYG_MACRO_START \
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334 if( _poldvsr_ != NULL ) \
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335 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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336 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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337 CYG_MACRO_END
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338
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339 // This is an ugly name, but what it means is: grab the VSR back to eCos
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340 // internal handling, or if you like, the default handler. But if
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341 // cooperating with GDB and CygMon, the default behaviour is to pass most
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342 // exceptions to CygMon. This macro undoes that so that eCos handles the
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343 // exception. So use it with care.
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344
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345 externC void cyg_hal_default_interrupt_vsr( void );
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346 externC void cyg_hal_default_exception_vsr( void );
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347 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
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348 CYG_MACRO_START \
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349 if( (void*)_poldvsr_ != (void*)NULL ) \
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350 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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351 hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
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352 ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
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353 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
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354 CYG_MACRO_END
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355
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356
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357 //--------------------------------------------------------------------------
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358 // Interrupt controller access
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359 //
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360 // Note: These macros work only on a unit basis ; if one source in a
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361 // unit (such as SCI) is unmasked, all sources of that unit get
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362 // unmasked. Finer control must be done in the driver/apps.
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363
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364 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
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365 externC cyg_uint8 cyg_hal_ILVL_table[];
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366 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \
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367 /* Update the ILVL table, so it is easy for the interrupt entry */ \
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diff changeset
368 /* code to find out the level of a given interrupt source. */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
369 cyg_hal_ILVL_table[(_vector_)] = (_level_)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
370 #else
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
371 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
372 #endif
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
373
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
374 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
375 CYG_MACRO_START \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
376 cyg_uint16 iprX; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
377 \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
378 CYG_ASSERT((0 <= (_level_) && 15 >= (_level_)), "Illegal level"); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
379 CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (_vector_) \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
380 && CYGNUM_HAL_ISR_MAX >= (_vector_)), "Illegal vector"); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
381 \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
382 HAL_UPDATE_ILVL_TABLE(_vector_, _level_); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
383 \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
384 switch( (_vector_) ) { \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
385 case CYGNUM_HAL_INTERRUPT_NMI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
386 /* fall through */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
387 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
388 /* Cannot change levels */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
389 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
390 \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
391 /* IPRA */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
392 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
393 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
394 iprX &= ~CYGARC_REG_IPRA_TMU0_MASK; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
395 iprX |= (_level_)*CYGARC_REG_IPRA_TMU0_PRI1; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
396 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
397 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
398 case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
399 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
400 iprX &= ~CYGARC_REG_IPRA_TMU1_MASK; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
401 iprX |= (_level_)*CYGARC_REG_IPRA_TMU1_PRI1; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
402 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
403 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
404 case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
405 case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
406 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
407 iprX &= ~CYGARC_REG_IPRA_TMU2_MASK; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
408 iprX |= (_level_)*CYGARC_REG_IPRA_TMU2_PRI1; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
409 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
410 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
411 case CYGNUM_HAL_INTERRUPT_RTC_ATI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
412 case CYGNUM_HAL_INTERRUPT_RTC_PRI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
413 case CYGNUM_HAL_INTERRUPT_RTC_CUI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
414 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
415 iprX &= ~CYGARC_REG_IPRA_RTC_MASK; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
416 iprX |= (_level_)*CYGARC_REG_IPRA_RTC_PRI1; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
417 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
418 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
419 \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
420 /* IPRB */ \
80
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
421 case CYGNUM_HAL_INTERRUPT_SCI_ERI: \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
422 case CYGNUM_HAL_INTERRUPT_SCI_RXI: \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
423 case CYGNUM_HAL_INTERRUPT_SCI_TXI: \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
424 case CYGNUM_HAL_INTERRUPT_SCI_TEI: \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
425 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
426 iprX &= ~CYGARC_REG_IPRB_SCI_MASK; \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
427 iprX |= (_level_)*CYGARC_REG_IPRB_SCI_PRI1; \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
428 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \
2085233a121a Merge from eCos master repository on 2000-04-07-07:52:29-BST
jlarmour
parents: 76
diff changeset
429 break; \
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
430 case CYGNUM_HAL_INTERRUPT_WDT_ITI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
431 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
432 iprX &= ~CYGARC_REG_IPRB_WDT_MASK; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
433 iprX |= (_level_)*CYGARC_REG_IPRB_WDT_PRI1; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
434 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
435 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
436 case CYGNUM_HAL_INTERRUPT_REF_RCMI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
437 case CYGNUM_HAL_INTERRUPT_REF_ROVI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
438 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
439 iprX &= ~CYGARC_REG_IPRB_REF_MASK; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
440 iprX |= (_level_)*CYGARC_REG_IPRB_REF_PRI1; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
441 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
442 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
443 \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
444 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
445 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
446 /* Do nothing for these reserved vectors. */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
447 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
448 } \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
449 CYG_MACRO_END
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
450
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
451
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
452 #define HAL_INTERRUPT_MASK( _vector_ ) \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
453 CYG_MACRO_START \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
454 switch( (_vector_) ) { \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
455 case CYGNUM_HAL_INTERRUPT_NMI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
456 /* fall through */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
457 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
458 /* Can only be masked by fiddling Imask in SR. */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
459 break; \
82
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents: 80
diff changeset
460 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: \
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
461 HAL_INTERRUPT_SET_LEVEL((_vector_), 0); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
462 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
463 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
464 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
465 /* Do nothing for these reserved vectors. */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
466 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
467 default: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
468 CYG_FAIL("Unknown interrupt vector"); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
469 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
470 } \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
471 CYG_MACRO_END
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
472
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
473 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
474 CYG_MACRO_START \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
475 switch( (_vector_) ) { \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
476 case CYGNUM_HAL_INTERRUPT_NMI: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
477 /* fall through */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
478 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
479 /* Can only be unmasked by fiddling Imask in SR. */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
480 break; \
82
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST
jlarmour
parents: 80
diff changeset
481 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX: \
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
482 HAL_INTERRUPT_SET_LEVEL((_vector_), 1); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
483 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
484 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
485 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
486 /* Do nothing for these reserved vectors. */ \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
487 break; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
488 default: \
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489 CYG_FAIL("Unknown interrupt vector"); \
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490 break; \
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491 } \
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492 CYG_MACRO_END
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493
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494 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
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495
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496 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
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497
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498 //--------------------------------------------------------------------------
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499 // Clock control
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500
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501 // Using TMU counter 0, clocked at p/4, with peripheral clock
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502 // sourced directly from the 15MHz crystal (which is the default setup
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503 // on the EDK). This means 150000/4 oscillations in 1/100 second.
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504 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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505 CYG_MACRO_START \
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506 register cyg_uint8 _tstr_; \
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507 \
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508 /* Disable timer while programming it. */ \
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509 HAL_READ_UINT8(CYGARC_REG_TSTR, _tstr_); \
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510 _tstr_ &= ~CYGARC_REG_TSTR_STR0; \
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511 HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_); \
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512 \
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513 /* Set counter registers. */ \
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514 HAL_WRITE_UINT32(CYGARC_REG_TCOR0, (_period_)); \
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515 HAL_WRITE_UINT32(CYGARC_REG_TCNT0, (_period_)); \
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516 \
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517 /* Set interrupt on underflow, decrement frequency at 1/4 of */ \
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518 /* peripheral clock. */ \
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519 HAL_WRITE_UINT16(CYGARC_REG_TCR0, CYGARC_REG_TCR_UNIE); \
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520 \
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521 /* Enable timer. */ \
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522 _tstr_ |= CYGARC_REG_TSTR_STR0; \
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523 HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_); \
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524 \
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525 CYG_MACRO_END
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526
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527 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
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528 CYG_MACRO_START \
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529 register cyg_uint16 _tcr_; \
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530 \
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531 /* Clear underflow flag. */ \
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532 HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_); \
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533 _tcr_ &= ~CYGARC_REG_TCR_UNF; \
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534 HAL_WRITE_UINT16(CYGARC_REG_TCR0, _tcr_); \
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535 HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_); \
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536 \
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537 CYG_MACRO_END
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538
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539 #define HAL_CLOCK_READ( _pvalue_ ) \
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540 CYG_MACRO_START \
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541 register cyg_uint32 _result_; \
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542 \
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543 HAL_READ_UINT32(CYGARC_REG_TCNT0, _result_); \
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544 \
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545 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-_result_; \
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546 CYG_MACRO_END
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547
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548 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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549 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
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550 #endif
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551
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552 #endif // __ASSEMBLER__
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553
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554 //--------------------------------------------------------------------------
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555 #endif // ifndef CYGONCE_HAL_INTR_H
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556 // End of hal_intr.h