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annotate packages/hal/sparclite/arch/current/include/hal_io.h @ 1777:c16341b1bac6 default tip
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| author | alexs |
|---|---|
| date | Mon, 12 Oct 2009 02:26:09 +0100 |
| parents | d2c90368aeef |
| children |
| rev | line source |
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| 2 | 1 #ifndef CYGONCE_HAL_IO_H |
| 2 #define CYGONCE_HAL_IO_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_io.h | |
| 7 // | |
| 8 // HAL device IO register support. | |
| 9 // | |
| 10 //============================================================================= | |
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11 //####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License along |
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26 // with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use macros |
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30 // or inline functions from this file, or you compile this file and link it |
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31 // with other works to produce a work based on this file, this file does not |
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32 // by itself cause the resulting work to be covered by the GNU General Public |
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33 // License. However the source code for this file must still be made available |
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34 // in accordance with section (3) of the GNU General Public License. |
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35 // |
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36 // This exception does not invalidate any other reasons why a work based on |
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37 // this file might be covered by the GNU General Public License. |
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38 // |
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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40 // at http://sources.redhat.com/ecos/ecos-license/ |
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41 // ------------------------------------------- |
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42 //####ECOSGPLCOPYRIGHTEND#### |
| 2 | 43 //============================================================================= |
| 44 //#####DESCRIPTIONBEGIN#### | |
| 45 // | |
| 46 // Author(s): nickg, hmt | |
| 47 // Contributors: nickg, hmt | |
| 48 // Date: 1998-02-17 | |
| 49 // Purpose: Define IO register support | |
| 50 // Description: The macros defined here provide the HAL APIs for handling | |
| 51 // device IO control registers. | |
| 52 // | |
| 53 // Usage: | |
| 54 // #include <cyg/hal/hal_io.h> | |
| 55 // ... | |
| 56 // | |
| 57 // | |
| 58 //####DESCRIPTIONEND#### | |
| 59 // | |
| 60 //============================================================================= | |
| 61 | |
| 62 #include <pkgconf/system.h> | |
| 63 | |
| 64 #include <cyg/infra/cyg_type.h> | |
| 65 | |
| 66 //----------------------------------------------------------------------------- | |
| 67 // Enforce in-order IO for all HAL reads/writes using this macro. | |
| 68 #define HAL_IO_BARRIER() \ | |
| 69 asm volatile ( "" : : : "memory" ) | |
| 70 | |
| 71 //----------------------------------------------------------------------------- | |
| 72 // IO Register address. | |
| 73 // This type is for recording the address of an IO register. | |
| 74 | |
| 75 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; | |
| 76 | |
| 77 //----------------------------------------------------------------------------- | |
| 78 // BYTE Register access. | |
| 79 // Individual and vectorized access to 8 bit registers. | |
| 80 | |
| 81 #define HAL_READ_UINT8( _register_, _value_ ) \ | |
| 82 CYG_MACRO_START \ | |
| 83 ((_value_) = *((volatile CYG_BYTE *)(_register_))); \ | |
| 84 HAL_IO_BARRIER (); \ | |
| 85 CYG_MACRO_END | |
| 86 | |
| 87 #define HAL_WRITE_UINT8( _register_, _value_ ) \ | |
| 88 CYG_MACRO_START \ | |
| 89 (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \ | |
| 90 HAL_IO_BARRIER (); \ | |
| 91 CYG_MACRO_END | |
| 92 | |
| 93 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 94 CYG_MACRO_START \ | |
| 95 cyg_count32 _i_,_j_; \ | |
| 96 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 97 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ | |
| 98 HAL_IO_BARRIER (); \ | |
| 99 } \ | |
| 100 CYG_MACRO_END | |
| 101 | |
| 102 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 103 CYG_MACRO_START \ | |
| 104 cyg_count32 _i_,_j_; \ | |
| 105 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 106 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ | |
| 107 HAL_IO_BARRIER (); \ | |
| 108 } \ | |
| 109 CYG_MACRO_END | |
| 110 | |
| 111 | |
| 112 //----------------------------------------------------------------------------- | |
| 113 // 16 bit access. | |
| 114 // Individual and vectorized access to 16 bit registers. | |
| 115 | |
| 116 #define HAL_READ_UINT16( _register_, _value_ ) \ | |
| 117 CYG_MACRO_START \ | |
| 118 ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \ | |
| 119 HAL_IO_BARRIER (); \ | |
| 120 CYG_MACRO_END | |
| 121 | |
| 122 #define HAL_WRITE_UINT16( _register_, _value_ ) \ | |
| 123 CYG_MACRO_START \ | |
| 124 (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \ | |
| 125 HAL_IO_BARRIER (); \ | |
| 126 CYG_MACRO_END | |
| 127 | |
| 128 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 129 CYG_MACRO_START \ | |
| 130 cyg_count32 _i_,_j_; \ | |
| 131 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 132 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ | |
| 133 HAL_IO_BARRIER (); \ | |
| 134 } \ | |
| 135 CYG_MACRO_END | |
| 136 | |
| 137 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 138 CYG_MACRO_START \ | |
| 139 cyg_count32 _i_,_j_; \ | |
| 140 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 141 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ | |
| 142 HAL_IO_BARRIER (); \ | |
| 143 } \ | |
| 144 CYG_MACRO_END | |
| 145 | |
| 146 //----------------------------------------------------------------------------- | |
| 147 // 32 bit access. | |
| 148 // Individual and vectorized access to 32 bit registers. | |
| 149 | |
| 150 #define HAL_READ_UINT32( _register_, _value_ ) \ | |
| 151 CYG_MACRO_START \ | |
| 152 ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \ | |
| 153 HAL_IO_BARRIER (); \ | |
| 154 CYG_MACRO_END | |
| 155 | |
| 156 #define HAL_WRITE_UINT32( _register_, _value_ ) \ | |
| 157 CYG_MACRO_START \ | |
| 158 (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \ | |
| 159 HAL_IO_BARRIER (); \ | |
| 160 CYG_MACRO_END | |
| 161 | |
| 162 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 163 CYG_MACRO_START \ | |
| 164 cyg_count32 _i_,_j_; \ | |
| 165 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 166 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ | |
| 167 HAL_IO_BARRIER (); \ | |
| 168 } \ | |
| 169 CYG_MACRO_END | |
| 170 | |
| 171 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ | |
| 172 CYG_MACRO_START \ | |
| 173 cyg_count32 _i_,_j_; \ | |
| 174 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ | |
| 175 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ | |
| 176 HAL_IO_BARRIER (); \ | |
| 177 } \ | |
| 178 CYG_MACRO_END | |
| 179 | |
| 180 //----------------------------------------------------------------------------- | |
| 181 | |
| 182 #ifndef CYGPKG_HAL_SPARCLITE_SIM | |
| 183 #include <cyg/hal/hal_hwio.h> | |
| 184 #endif // Not the SPARClite simulator | |
| 185 | |
| 186 #endif // ifndef CYGONCE_HAL_IO_H | |
| 187 // End of hal_io.h |