new file mode 100644
--- /dev/null
+++ b/packages/hal/sparclite/arch/current/include/hal_io.h
@@ -0,0 +1,176 @@
+#ifndef CYGONCE_HAL_IO_H
+#define CYGONCE_HAL_IO_H
+
+//=============================================================================
+//
+//      hal_io.h
+//
+//      HAL device IO register support.
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// The contents of this file are subject to the Cygnus eCos Public License
+// Version 1.0 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://sourceware.cygnus.com/ecos
+// 
+// Software distributed under the License is distributed on an "AS IS"
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
+// License for the specific language governing rights and limitations under
+// the License.
+// 
+// The Original Code is eCos - Embedded Cygnus Operating System, released
+// September 30, 1998.
+// 
+// The Initial Developer of the Original Code is Cygnus.  Portions created
+// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved.
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, hmt
+// Contributors:        nickg, hmt
+// Date:        1998-02-17
+// Purpose:     Define IO register support
+// Description: The macros defined here provide the HAL APIs for handling
+//              device IO control registers.
+//              
+// Usage:
+//              #include <cyg/hal/hal_io.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Enforce in-order IO for all HAL reads/writes using this macro.
+#define HAL_IO_BARRIER()                        \
+    asm volatile ( "" : : : "memory" )
+
+//-----------------------------------------------------------------------------
+// IO Register address.
+// This type is for recording the address of an IO register.
+
+typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
+
+//-----------------------------------------------------------------------------
+// BYTE Register access.
+// Individual and vectorized access to 8 bit registers.
+
+#define HAL_READ_UINT8( _register_, _value_ )           \
+    CYG_MACRO_START                                     \
+    ((_value_) = *((volatile CYG_BYTE *)(_register_))); \
+    HAL_IO_BARRIER ();                                  \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8( _register_, _value_ )          \
+    CYG_MACRO_START                                     \
+    (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
+    HAL_IO_BARRIER ();                                  \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
+        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \
+        HAL_IO_BARRIER ();                                              \
+    }                                                                   \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
+        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \
+        HAL_IO_BARRIER ();                                              \
+    }                                                                   \
+    CYG_MACRO_END
+
+
+//-----------------------------------------------------------------------------
+// 16 bit access.
+// Individual and vectorized access to 16 bit registers.
+    
+#define HAL_READ_UINT16( _register_, _value_ )                  \
+    CYG_MACRO_START                                             \
+    ((_value_) = *((volatile CYG_WORD16 *)(_register_)));       \
+    HAL_IO_BARRIER ();                                          \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16( _register_, _value_ )                 \
+    CYG_MACRO_START                                             \
+    (*((volatile CYG_WORD16 *)(_register_)) = (_value_));       \
+    HAL_IO_BARRIER ();                                          \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
+        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \
+        HAL_IO_BARRIER ();                                              \
+    }                                                                   \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
+        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \
+        HAL_IO_BARRIER ();                                              \
+    }                                                                   \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// 32 bit access.
+// Individual and vectorized access to 32 bit registers.
+    
+#define HAL_READ_UINT32( _register_, _value_ )                  \
+    CYG_MACRO_START                                             \
+    ((_value_) = *((volatile CYG_WORD32 *)(_register_)));       \
+    HAL_IO_BARRIER ();                                          \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT32( _register_, _value_ )                 \
+    CYG_MACRO_START                                             \
+    (*((volatile CYG_WORD32 *)(_register_)) = (_value_));       \
+    HAL_IO_BARRIER ();                                          \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
+        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \
+        HAL_IO_BARRIER ();                                              \
+    }                                                                   \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
+        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \
+        HAL_IO_BARRIER ();                                              \
+    }                                                                   \
+    CYG_MACRO_END
+    
+//-----------------------------------------------------------------------------
+
+#ifndef CYGPKG_HAL_SPARCLITE_SIM
+#include <cyg/hal/hal_hwio.h>
+#endif // Not the SPARClite simulator
+
+#endif // ifndef CYGONCE_HAL_IO_H
+// End of hal_io.h