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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents c0ed1c4642f8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*=================================================================
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2 //
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3 // kcache2.c
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4 //
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5 // Cache feature/timing tests
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 // Copyright (C) 2003 Gary Thomas
208
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13 //
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14 // eCos is free software; you can redistribute it and/or modify it under
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15 // the terms of the GNU General Public License as published by the Free
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16 // Software Foundation; either version 2 or (at your option) any later version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License along
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24 // with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use macros
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28 // or inline functions from this file, or you compile this file and link it
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29 // with other works to produce a work based on this file, this file does not
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30 // by itself cause the resulting work to be covered by the GNU General Public
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31 // License. However the source code for this file must still be made available
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32 // in accordance with section (3) of the GNU General Public License.
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33 //
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34 // This exception does not invalidate any other reasons why a work based on
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35 // this file might be covered by the GNU General Public License.
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36 //
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37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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38 // at http://sources.redhat.com/ecos/ecos-license/
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39 // -------------------------------------------
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40 //####ECOSGPLCOPYRIGHTEND####
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41 //==========================================================================
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42 //#####DESCRIPTIONBEGIN####
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43 //
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44 // Author(s): jskov, based on kcache1.c by dsm
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45 // Contributors: jskov, gthomas
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46 // Date: 1998-12-10
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47 // Description: Tests some of the more exotic cache macros.
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48 //####DESCRIPTIONEND####
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49 */
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50
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51 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL
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52
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53 #include <cyg/kernel/kapi.h>
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54
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55 #include <cyg/infra/testcase.h>
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56
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57 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK
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58 #ifdef CYGFUN_KERNEL_API_C
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59
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60 #include <cyg/infra/diag.h>
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61 #include <cyg/hal/hal_cache.h>
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62
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63 // -------------------------------------------------------------------------
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64
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65 #define NTHREADS 1
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66 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
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67
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68 // The following are defaults for loop variables. Note they will be overriden
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69 // on simulator targets, where detected - there is no point testing a cache
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70 // which doesn't exist :-).
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71
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72 #define TEST_DZERO_LOOPS 5000 // default number of loops for test_dzero()
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73 #define TIME_ILOCK_LOOPS 10000 // default number of loops for time_ilock()
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74 #define TIME_DLOCK_LOOPS 10000 // default number of loops for time_dlock()
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75
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76 // Define this to enable a simple, but hopefully useful, data cache
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77 // test. It may help discover if the cache support has been defined
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78 // properly (in terms of size and shape)
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79 #ifdef HAL_DCACHE_LINE_SIZE
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80 #define _TEST_DCACHE_OPERATION
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81 #endif
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82
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83 static cyg_handle_t thread[NTHREADS];
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84
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85 static cyg_thread thread_obj[NTHREADS];
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86 static char stack[NTHREADS][STACKSIZE];
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87
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88 #define MAXSIZE 1<<18
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89
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90 volatile char m[MAXSIZE];
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91
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92 // -------------------------------------------------------------------------
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93 // Test of data cache zero.
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94 // o Timing comparison with instructions doing the same amount of work.
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95 // o Check that area cleared with the DCACHE_ZERO macro contains zeros.
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96 #ifdef HAL_DCACHE_ZERO
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97 static void test_dzero(void)
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98 {
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99 register cyg_uint32 k, i;
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100 cyg_tick_count_t count0, count1;
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101 cyg_ucount32 t;
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102 volatile cyg_uint32* aligned_p;
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103 volatile cyg_uint32* p;
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104 register CYG_INTERRUPT_STATE oldints;
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105 cyg_ucount32 test_dzero_loops = TEST_DZERO_LOOPS;
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106
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107 CYG_TEST_INFO("Data cache zero");
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108
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109 if (cyg_test_is_simulator)
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110 test_dzero_loops=10;
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111
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112 aligned_p = (volatile cyg_uint32*)
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113 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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114 & ~(HAL_DCACHE_LINE_SIZE-1));
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115
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116 // Time with conventional instructions.
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117 HAL_DISABLE_INTERRUPTS(oldints);
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118 HAL_DCACHE_SYNC();
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119 HAL_DCACHE_DISABLE();
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120 HAL_DCACHE_SYNC();
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121 HAL_DCACHE_INVALIDATE_ALL();
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122 HAL_DCACHE_ENABLE();
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123 HAL_RESTORE_INTERRUPTS(oldints);
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124 count0 = cyg_current_time();
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125 for (k = 0; k < test_dzero_loops; k++) {
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126 p = aligned_p;
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127 for (i = 0; i < HAL_DCACHE_SETS; i++) {
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128 #if (16 == HAL_DCACHE_LINE_SIZE)
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129 *p++ = 0;
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130 *p++ = 0;
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131 *p++ = 0;
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132 *p++ = 0;
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133 #elif (32 == HAL_DCACHE_LINE_SIZE)
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134 *p++ = 0;
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135 *p++ = 0;
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136 *p++ = 0;
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137 *p++ = 0;
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138 *p++ = 0;
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139 *p++ = 0;
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140 *p++ = 0;
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141 *p++ = 0;
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142 #else
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143 #error "Not defined for this cache line size."
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144 #endif
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145 }
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146
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147 HAL_DISABLE_INTERRUPTS(oldints);
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148 HAL_DCACHE_SYNC();
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149 HAL_DCACHE_DISABLE();
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150 HAL_DCACHE_SYNC();
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151 HAL_DCACHE_INVALIDATE_ALL();
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152 HAL_DCACHE_ENABLE();
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153 HAL_RESTORE_INTERRUPTS(oldints);
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154 }
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155 count1 = cyg_current_time();
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156 t = count1 - count0;
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157 diag_printf("time with instructions: %d\n", t);
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158
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159 // Initialize the area with non-zero so we can check whether
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160 // the macro cleared the area properly.
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161 p = aligned_p;
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162 for (i = 0;
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163 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32);
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164 i++) {
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165 *p++ = 0xdeadbeef;
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166 }
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167
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168 // Time with DCACHE_ZERO.
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169 HAL_DISABLE_INTERRUPTS(oldints);
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170 HAL_DCACHE_SYNC();
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171 HAL_DCACHE_DISABLE();
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172 HAL_DCACHE_SYNC();
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173 HAL_DCACHE_INVALIDATE_ALL();
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174 HAL_DCACHE_ENABLE();
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175 HAL_RESTORE_INTERRUPTS(oldints);
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176 count0 = cyg_current_time();
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177 for (k = 0; k < test_dzero_loops; k++) {
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178 HAL_DCACHE_ZERO(aligned_p, HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE);
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179
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180 HAL_DISABLE_INTERRUPTS(oldints);
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181 HAL_DCACHE_SYNC();
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182 HAL_DCACHE_DISABLE();
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183 HAL_DCACHE_SYNC();
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184 HAL_DCACHE_INVALIDATE_ALL();
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185 HAL_DCACHE_ENABLE();
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186 HAL_RESTORE_INTERRUPTS(oldints);
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187 }
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188 count1 = cyg_current_time();
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189 t = count1 - count0;
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190 diag_printf("time with HAL_DCACHE_ZERO: %d\n", t);
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191
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192 // Verify that the area was actually cleared.
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193 {
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194 cyg_uint32 d;
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195
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196 d = 0;
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197 p = aligned_p;
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198 for (i = 0;
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199 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32);
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200 i++) {
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201 d |= *p++;
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202 }
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203
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204 CYG_TEST_CHECK(0 == d, "region not properly cleared");
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205 }
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206
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207 }
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208 #endif
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209
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210 // -------------------------------------------------------------------------
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211 // Test of data cache write hint.
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212 // Just check that the macro compiles.
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213 #ifdef HAL_DCACHE_WRITE_HINT
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214 static void test_dwrite_hint(void)
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215 {
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216 register cyg_uint32 k;
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217 register CYG_INTERRUPT_STATE oldints;
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218
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219 CYG_TEST_INFO("Data cache write hint");
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220
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221 HAL_DISABLE_INTERRUPTS(oldints);
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222 HAL_DCACHE_SYNC();
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223 HAL_DCACHE_DISABLE();
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224 HAL_DCACHE_SYNC();
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225 HAL_DCACHE_INVALIDATE_ALL();
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226 HAL_DCACHE_ENABLE();
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227 HAL_RESTORE_INTERRUPTS(oldints);
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228
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229 HAL_DCACHE_WRITE_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE);
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230 for (k = 0; k < 20; k++);
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231 m[HAL_DCACHE_LINE_SIZE*2] = 42;
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232 }
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233 #endif
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234
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235 // -------------------------------------------------------------------------
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236 // Test of data cache read hint.
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237 // Just check that the macro compiles.
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238 #ifdef HAL_DCACHE_READ_HINT
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239 static void test_dread_hint(void)
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240 {
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241 register char c;
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242 register cyg_uint32 k;
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243 register CYG_INTERRUPT_STATE oldints;
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244
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245 CYG_TEST_INFO("Data cache read hint");
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246
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247 HAL_DISABLE_INTERRUPTS(oldints);
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248 HAL_DCACHE_SYNC();
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249 HAL_DCACHE_DISABLE();
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250 HAL_DCACHE_SYNC();
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251 HAL_DCACHE_INVALIDATE_ALL();
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252 HAL_DCACHE_ENABLE();
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253 HAL_RESTORE_INTERRUPTS(oldints);
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254
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255 HAL_DCACHE_READ_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE);
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256 for (k = 0; k < 20; k++);
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257 c = m[HAL_DCACHE_LINE_SIZE*2];
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258 }
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259 #endif
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260
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261 // -------------------------------------------------------------------------
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262 // Test of data cache line store
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263 // o No semantic requirement.
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264 // o Check that flushed data is written to memory.
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265 // o Simple invocation check of macro.
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266 #ifdef HAL_DCACHE_STORE
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267 static void test_dstore(void)
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268 {
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269 volatile cyg_uint8* aligned_p;
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270 cyg_int32 i;
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271 register CYG_INTERRUPT_STATE oldints;
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272
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273 CYG_TEST_INFO("Data cache store region");
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274
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275 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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276 m[i] = 0;
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277
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278 HAL_DISABLE_INTERRUPTS(oldints);
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279 HAL_DCACHE_SYNC();
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280 HAL_DCACHE_DISABLE();
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281 HAL_DCACHE_SYNC();
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282 HAL_DCACHE_INVALIDATE_ALL();
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283 HAL_DCACHE_ENABLE();
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284
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285 aligned_p = (volatile cyg_uint8*)
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286 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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287 & ~(HAL_DCACHE_LINE_SIZE-1));
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288
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289 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
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290
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291 HAL_DCACHE_STORE(aligned_p, HAL_DCACHE_LINE_SIZE);
143
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292
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293 CYG_TEST_CHECK(42 == aligned_p[0],
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294 "memory didn't contain flushed data");
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295
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296 HAL_DCACHE_INVALIDATE_ALL(); // Discard...
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297
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298 CYG_TEST_CHECK(42 == aligned_p[0],
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299 "memory didn't contain flushed data after invalidate all");
208
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300
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301 HAL_RESTORE_INTERRUPTS(oldints);
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302 }
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303 #endif
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304
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305 // -------------------------------------------------------------------------
143
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306 // Test of data cache total flush (sync).
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307 // o No semantic requirement.
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308 // o Check that flushed data is written to memory.
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309 // o Simple invocation check of macro.
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310 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory
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311
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312 #ifdef _TEST_DCACHE_OPERATION
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313 static void
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314 test_dcache_operation(void)
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315 {
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316 long *lp = (long *)m;
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317 int i, errs;
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318 cyg_uint32 oldints;
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319
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320 CYG_TEST_INFO("Data cache basic");
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321
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322 HAL_DISABLE_INTERRUPTS(oldints);
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323 HAL_DCACHE_SYNC();
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324 HAL_DCACHE_DISABLE();
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325 HAL_DCACHE_SYNC();
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326 // Fill test buffer
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327 for (i = 0; i < sizeof(m)/sizeof(*lp); i++) {
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328 lp[i] = i;
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329 }
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330 HAL_DCACHE_INVALIDATE_ALL();
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331 HAL_DCACHE_ENABLE();
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332 // Now push data through the cache
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333 // Note: 256 seems like a reasonable offset. It may be useful to actually
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334 // compute this (and the size of the test region) based on cache geometry
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335 for (i = 256; i < 256+HAL_DCACHE_SIZE/sizeof(*lp); i++) {
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336 lp[i] = 0xFF000000 + i;
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337 }
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338 // Now force cache clean and off
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339 HAL_DCACHE_SYNC();
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340 HAL_DCACHE_DISABLE();
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341 // Verify the data
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342 diag_printf("Verify data with cache off\n");
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343 errs = 0;
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344 for (i = 0; i < sizeof(m)/sizeof(*lp); i++) {
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345 if ((i >= 256) && (i < 256+HAL_DCACHE_SIZE/sizeof(*lp))) {
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346 if (lp[i] != (0xFF000000 + i)) {
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347 if (++errs < 16) {
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348 diag_printf("Data inside test range changed - was: %x, is %x, index: %x\n",
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349 0xFF000000+i, lp[i], i);
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350 }
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351 }
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352 } else {
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353 if (lp[i] != i) {
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354 if (++errs < 16) {
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355 diag_printf("Data outside test range changed - was: %x, is %x, index: %x\n",
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356 i, lp[i], i);
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357 }
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358 }
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359 }
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360 }
583
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361 CYG_TEST_CHECK(0 == errs, "dcache basic failed");
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362 #if 0 // Additional information
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363 diag_printf("%d total errors during compare\n", errs);
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364 diag_dump_buf(&lp[240], 128);
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365 #endif
477
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366 HAL_RESTORE_INTERRUPTS(oldints);
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367 }
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368 #endif
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369
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370 static void test_dsync(void)
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371 {
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372 volatile cyg_uint8* aligned_p;
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373 cyg_int32 i;
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374 register CYG_INTERRUPT_STATE oldints;
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375
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376 CYG_TEST_INFO("Data cache sync all");
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377
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378 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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379 m[i] = 0;
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380
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381 HAL_DISABLE_INTERRUPTS(oldints);
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382 HAL_DCACHE_SYNC();
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383 HAL_DCACHE_DISABLE();
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384 HAL_DCACHE_SYNC();
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385 HAL_DCACHE_INVALIDATE_ALL();
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386 HAL_DCACHE_ENABLE();
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387
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388 aligned_p = (volatile cyg_uint8*)
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389 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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390 & ~(HAL_DCACHE_LINE_SIZE-1));
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391
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392 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
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393 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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394
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395 HAL_DCACHE_SYNC();
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396
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397 CYG_TEST_CHECK(42 == aligned_p[0],
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398 "memory didn't contain flushed data");
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399 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
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400 "memory didn't contain flushed data next block");
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401
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402 HAL_DCACHE_INVALIDATE_ALL();
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403
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404 CYG_TEST_CHECK(42 == aligned_p[0],
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405 "memory didn't contain flushed data after invalidate");
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406 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
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407 "memory didn't contain flushed data next block after invalidate");
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408
208
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409 HAL_RESTORE_INTERRUPTS(oldints);
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410
195
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411 HAL_ICACHE_INVALIDATE_ALL();
143
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412 HAL_DCACHE_DISABLE();
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413
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414 CYG_TEST_CHECK(42 == aligned_p[0],
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415 "memory didn't contain flushed data after disable");
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416 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
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417 "memory didn't contain flushed data next block after disable");
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418
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419 HAL_DCACHE_ENABLE();
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420 }
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421 #endif // HAL_DCACHE_LINE_SIZE
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422
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423 // -------------------------------------------------------------------------
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424 // Test of data cache line flush.
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425 // o Requires write-back cache.
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426 // o Check that flushed data is written to memory.
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427 // o Simple range check of macro.
191
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428 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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429 #ifdef HAL_DCACHE_FLUSH
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430 static void test_dflush(void)
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431 {
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432 volatile cyg_uint8* aligned_p;
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433 cyg_int32 i;
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434 register CYG_INTERRUPT_STATE oldints;
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435
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436 CYG_TEST_INFO("Data cache flush region");
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437
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438 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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439 m[i] = 0;
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440
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441 HAL_DISABLE_INTERRUPTS(oldints);
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442 HAL_DCACHE_SYNC();
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443 HAL_DCACHE_DISABLE();
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444 HAL_DCACHE_SYNC();
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445 HAL_DCACHE_INVALIDATE_ALL();
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446 HAL_DCACHE_ENABLE();
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447 HAL_RESTORE_INTERRUPTS(oldints);
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448
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449 aligned_p = (volatile cyg_uint8*)
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450 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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451 & ~(HAL_DCACHE_LINE_SIZE-1));
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452
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453 HAL_DISABLE_INTERRUPTS(oldints);
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diff changeset
454
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455 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
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456 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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457
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458 HAL_DCACHE_FLUSH(aligned_p, HAL_DCACHE_LINE_SIZE);
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459
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460 HAL_DCACHE_DISABLE();
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461
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462 HAL_RESTORE_INTERRUPTS(oldints);
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463
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464 CYG_TEST_CHECK(42 == aligned_p[0],
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465 "memory didn't contain flushed data");
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466 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
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467 "flushed beyond region");
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468
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469 HAL_DCACHE_ENABLE();
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470 }
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471 #endif
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472 #endif
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473
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474 // -------------------------------------------------------------------------
143
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475 // Test of data cache disable (which does NOT force contents out to RAM)
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476 // o Requires write-back cache [so NOT invoked unconditionally]
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477 // o Check that dirty data is not written to memory and is invalidated
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478 // in the cache.
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479 // o Simple invocation check of macro.
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480 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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481 static void test_ddisable(void)
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482 {
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483 volatile cyg_uint8* aligned_p;
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484 cyg_int32 i;
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485 register CYG_INTERRUPT_STATE oldints;
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486
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487 CYG_TEST_INFO("Data cache gross disable");
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diff changeset
488
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489 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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490 m[i] = 0;
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491
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492 HAL_DISABLE_INTERRUPTS(oldints);
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493 HAL_DCACHE_SYNC();
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494 HAL_DCACHE_DISABLE();
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495 HAL_DCACHE_SYNC();
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496 HAL_DCACHE_INVALIDATE_ALL();
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497 HAL_DCACHE_ENABLE();
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498 HAL_RESTORE_INTERRUPTS(oldints);
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499
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500 aligned_p = (volatile cyg_uint8*)
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501 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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502 & ~(HAL_DCACHE_LINE_SIZE-1));
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503
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504 HAL_DISABLE_INTERRUPTS(oldints);
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505
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506 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
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507 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
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508
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509 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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diff changeset
510
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511 HAL_DCACHE_DISABLE();
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512
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513 HAL_RESTORE_INTERRUPTS(oldints);
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514
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515 CYG_TEST_CHECK(0 == aligned_p[0] &&
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516 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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517 "cache/memory contained invalidated data");
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518 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
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519 "next block contained invalidated data");
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520
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521 HAL_DCACHE_ENABLE();
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522 }
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523 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
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524
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525 // -------------------------------------------------------------------------
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526 // Test of data cache total invalidate.
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527 // o Requires write-back cache.
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528 // o Check that invalidated data is not written to memory and is invalidated
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529 // in the cache.
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530 // o Simple invocation check of macro.
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diff changeset
531 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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532 #ifdef HAL_DCACHE_INVALIDATE_ALL
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533 static void test_dinvalidate_all(void)
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534 {
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535 volatile cyg_uint8* aligned_p;
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536 cyg_int32 i;
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537 register CYG_INTERRUPT_STATE oldints;
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538
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539 CYG_TEST_INFO("Data cache invalidate all");
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540
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541 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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542 m[i] = 0;
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diff changeset
543
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544 HAL_DISABLE_INTERRUPTS(oldints);
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545 HAL_DCACHE_SYNC();
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diff changeset
546 HAL_DCACHE_DISABLE();
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diff changeset
547 HAL_DCACHE_SYNC();
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548 HAL_DCACHE_INVALIDATE_ALL();
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549 HAL_DCACHE_ENABLE();
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550
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551 aligned_p = (volatile cyg_uint8*)
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552 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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553 & ~(HAL_DCACHE_LINE_SIZE-1));
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554
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555 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
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556 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
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diff changeset
557
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558 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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diff changeset
559
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560 HAL_DCACHE_INVALIDATE_ALL();
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561
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562 HAL_RESTORE_INTERRUPTS(oldints);
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563
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564 CYG_TEST_CHECK(0 == aligned_p[0] &&
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565 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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566 "cache/memory contained invalidated data");
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567 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
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568 "next block contained invalidated data");
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569 }
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570 #endif
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571 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
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572
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573 // -------------------------------------------------------------------------
2
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574 // Test of data cache line invalidate.
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575 // o Requires write-back cache.
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576 // o Check that invalidated data is not written to memory and is invalidated
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577 // in the cache.
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578 // o Simple range check of macro.
143
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579 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
2
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580 #ifdef HAL_DCACHE_INVALIDATE
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581 static void test_dinvalidate(void)
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582 {
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583 volatile cyg_uint8* aligned_p;
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584 cyg_int32 i;
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585 register CYG_INTERRUPT_STATE oldints;
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586
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587 CYG_TEST_INFO("Data cache invalidate region");
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588
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589 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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590 m[i] = 0;
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591
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592 HAL_DISABLE_INTERRUPTS(oldints);
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593 HAL_DCACHE_SYNC();
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594 HAL_DCACHE_DISABLE();
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595 HAL_DCACHE_SYNC();
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596 HAL_DCACHE_INVALIDATE_ALL();
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597 HAL_DCACHE_ENABLE();
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598 HAL_RESTORE_INTERRUPTS(oldints);
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599
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600 aligned_p = (volatile cyg_uint8*)
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601 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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602 & ~(HAL_DCACHE_LINE_SIZE-1));
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603
143
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604 HAL_DISABLE_INTERRUPTS(oldints);
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diff changeset
605
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606 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
2
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607 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
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608
143
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609 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
2
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610
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611 HAL_DCACHE_INVALIDATE(aligned_p, HAL_DCACHE_LINE_SIZE);
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612
143
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613 HAL_RESTORE_INTERRUPTS(oldints);
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614
2
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615 CYG_TEST_CHECK(0 == aligned_p[0] &&
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616 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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617 "cache/memory contained invalidated data");
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618 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE],
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619 "invalidated beyond range");
143
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620
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621 HAL_DCACHE_SYNC();
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622 HAL_DCACHE_DISABLE();
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623
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624 CYG_TEST_CHECK(0 == aligned_p[0] &&
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625 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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626 "cache/memory contained invalidated data after SYNC/DIS");
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diff changeset
627 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE],
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
628 "invalidated beyond range after SYNC/DIS");
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
629
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
630 HAL_DCACHE_ENABLE();
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
631 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
632 #endif
143
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
633 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
634
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
635 // -------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
636 // Test of instruction cache locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
637 // o Time difference between repeatedly executing a bunch of instructions
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
638 // with and without locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
639 #ifdef HAL_ICACHE_LOCK
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
640 static void iloop(unsigned long* start, unsigned long* end, int dummy)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
641 {
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
642 // dummy is just used to fool the compiler to not move the labels
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
643 // around. All callers should call with dummy=0;
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
644
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
645 register char c;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
646 register CYG_INTERRUPT_STATE oldints;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
647
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
648 if (1 == dummy) goto label_end;
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
649
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
650 label_start:
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
651 // Invalidating shouldn't affect locked lines.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
652 HAL_DISABLE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
653 HAL_ICACHE_DISABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
654 HAL_ICACHE_INVALIDATE_ALL();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
655 HAL_ICACHE_ENABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
656 HAL_RESTORE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
657
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
658 c = m[HAL_DCACHE_LINE_SIZE*0];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
659 c = m[HAL_DCACHE_LINE_SIZE*1];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
660 c = m[HAL_DCACHE_LINE_SIZE*2];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
661 c = m[HAL_DCACHE_LINE_SIZE*3];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
662 c = m[HAL_DCACHE_LINE_SIZE*4];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
663 c = m[HAL_DCACHE_LINE_SIZE*5];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
664 c = m[HAL_DCACHE_LINE_SIZE*6];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
665 c = m[HAL_DCACHE_LINE_SIZE*7];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
666 c = m[HAL_DCACHE_LINE_SIZE*8];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
667 c = m[HAL_DCACHE_LINE_SIZE*9];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
668 c = m[HAL_DCACHE_LINE_SIZE*10];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
669 c = m[HAL_DCACHE_LINE_SIZE*11];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
670 c = m[HAL_DCACHE_LINE_SIZE*12];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
671 c = m[HAL_DCACHE_LINE_SIZE*13];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
672 c = m[HAL_DCACHE_LINE_SIZE*14];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
673 c = m[HAL_DCACHE_LINE_SIZE*15];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
674 c = m[HAL_DCACHE_LINE_SIZE*16];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
675 c = m[HAL_DCACHE_LINE_SIZE*17];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
676 c = m[HAL_DCACHE_LINE_SIZE*18];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
677 c = m[HAL_DCACHE_LINE_SIZE*19];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
678 c = m[HAL_DCACHE_LINE_SIZE*20];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
679 c = m[HAL_DCACHE_LINE_SIZE*21];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
680 c = m[HAL_DCACHE_LINE_SIZE*22];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
681 c = m[HAL_DCACHE_LINE_SIZE*23];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
682 c = m[HAL_DCACHE_LINE_SIZE*24];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
683 c = m[HAL_DCACHE_LINE_SIZE*25];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
684 c = m[HAL_DCACHE_LINE_SIZE*26];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
685 c = m[HAL_DCACHE_LINE_SIZE*27];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
686 c = m[HAL_DCACHE_LINE_SIZE*28];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
687 c = m[HAL_DCACHE_LINE_SIZE*29];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
688 c = m[HAL_DCACHE_LINE_SIZE*30];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
689 c = m[HAL_DCACHE_LINE_SIZE*31];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
690 c = m[HAL_DCACHE_LINE_SIZE*32];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
691 c = m[HAL_DCACHE_LINE_SIZE*33];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
692 c = m[HAL_DCACHE_LINE_SIZE*34];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
693 c = m[HAL_DCACHE_LINE_SIZE*35];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
694 c = m[HAL_DCACHE_LINE_SIZE*36];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
695 c = m[HAL_DCACHE_LINE_SIZE*37];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
696 c = m[HAL_DCACHE_LINE_SIZE*38];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
697 c = m[HAL_DCACHE_LINE_SIZE*39];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
698 c = m[HAL_DCACHE_LINE_SIZE*40];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
699 c = m[HAL_DCACHE_LINE_SIZE*41];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
700 c = m[HAL_DCACHE_LINE_SIZE*42];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
701 c = m[HAL_DCACHE_LINE_SIZE*43];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
702 c = m[HAL_DCACHE_LINE_SIZE*44];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
703 c = m[HAL_DCACHE_LINE_SIZE*45];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
704 c = m[HAL_DCACHE_LINE_SIZE*46];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
705 c = m[HAL_DCACHE_LINE_SIZE*47];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
706 c = m[HAL_DCACHE_LINE_SIZE*48];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
707 c = m[HAL_DCACHE_LINE_SIZE*49];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
708 c = m[HAL_DCACHE_LINE_SIZE*50];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
709 c = m[HAL_DCACHE_LINE_SIZE*51];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
710 c = m[HAL_DCACHE_LINE_SIZE*52];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
711 c = m[HAL_DCACHE_LINE_SIZE*53];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
712 c = m[HAL_DCACHE_LINE_SIZE*54];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
713 c = m[HAL_DCACHE_LINE_SIZE*55];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
714 c = m[HAL_DCACHE_LINE_SIZE*56];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
715 c = m[HAL_DCACHE_LINE_SIZE*57];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
716 c = m[HAL_DCACHE_LINE_SIZE*58];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
717 c = m[HAL_DCACHE_LINE_SIZE*59];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
718 c = m[HAL_DCACHE_LINE_SIZE*60];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
719 c = m[HAL_DCACHE_LINE_SIZE*61];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
720 c = m[HAL_DCACHE_LINE_SIZE*62];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
721 c = m[HAL_DCACHE_LINE_SIZE*63];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
722
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
723 label_end:
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
724
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
725 *start = (unsigned long) &&label_start;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
726 *end = (unsigned long) &&label_end;
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
727
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
728 if (1 == dummy) goto label_start;
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
729 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
730
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
731 static void time_ilock(void)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
732 {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
733 register cyg_ucount32 k;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
734 cyg_tick_count_t count0, count1;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
735 cyg_ucount32 t;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
736 unsigned long start, end;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
737 register cyg_ucount32 time_ilock_loops = TIME_ILOCK_LOOPS;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
738
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
739 CYG_TEST_INFO("Instruction cache lock");
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
740
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
741 if (cyg_test_is_simulator)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
742 time_ilock_loops = 10;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
743
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
744 count0 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
745 for (k = 0; k < time_ilock_loops; k++) {
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
746 iloop(&start, &end, 0);
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
747 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
748 count1 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
749 t = count1 - count0;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
750 diag_printf("time without lock: %d\n", t);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
751
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
752 HAL_ICACHE_LOCK(start, end-start);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
753
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
754 count0 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
755 for (k = 0; k < time_ilock_loops; k++) {
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
756 iloop(&start, &end, 0);
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
757 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
758 count1 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
759 t = count1 - count0;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
760 diag_printf("time with lock: %d\n", t);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
761
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
762 HAL_ICACHE_UNLOCK(start, end-start);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
763 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
764 #endif // ifdef HAL_ICACHE_LOCK
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
765
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
766 // -------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
767 // Test of data cache locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
768 // o Time difference between repeatedly accessing a memory region
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
769 // with and without locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
770 #ifdef HAL_DCACHE_LOCK
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
771 static void dloop(void)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
772 {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
773 register cyg_uint32 j;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
774 register char c;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
775 register CYG_INTERRUPT_STATE oldints;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
776
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
777 HAL_DISABLE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
778 HAL_DCACHE_SYNC();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
779 HAL_DCACHE_DISABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
780 HAL_DCACHE_SYNC();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
781 HAL_DCACHE_INVALIDATE_ALL();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
782 HAL_DCACHE_ENABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
783 HAL_RESTORE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
784 for (j = 0; j < HAL_DCACHE_SETS; j++) {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
785 c = m[HAL_DCACHE_LINE_SIZE*j];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
786 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
787 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
788
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
789 static void time_dlock(void)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
790 {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
791 register cyg_ucount32 k;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
792 cyg_tick_count_t count0, count1;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
793 cyg_ucount32 t;
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794 register cyg_ucount32 time_dlock_loops = TIME_DLOCK_LOOPS;
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795
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796 CYG_TEST_INFO("Data cache lock");
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797
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798 if (cyg_test_is_simulator)
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799 time_dlock_loops = 10;
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800
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801 count0 = cyg_current_time();
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802 for (k = 0; k < time_dlock_loops; k++) {
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diff changeset
803 dloop();
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804 }
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805 count1 = cyg_current_time();
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806 t = count1 - count0;
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807 diag_printf("time without lock: %d\n", t);
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808
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809 HAL_DCACHE_LOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE);
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810
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811 count0 = cyg_current_time();
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812 for (k = 0; k < time_dlock_loops; k++) {
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813 dloop();
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814 }
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815 count1 = cyg_current_time();
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816 t = count1 - count0;
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817 diag_printf("time with lock: %d\n", t);
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818
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819 HAL_DCACHE_UNLOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE);
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820 }
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821 #endif // ifdef HAL_DCACHE_LOCK
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822
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823 // -------------------------------------------------------------------------
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824 static void entry0( cyg_addrword_t data )
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825 {
143
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826 int numtests = 0;
24
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827 #ifdef HAL_DCACHE_QUERY_WRITE_MODE
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diff changeset
828 int wmode;
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829 #endif
2
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830 #ifdef HAL_DCACHE_LOCK
143
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831 time_dlock(); numtests++;
2
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832 #endif
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833 #ifdef HAL_ICACHE_LOCK
143
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834 time_ilock(); numtests++;
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835 #endif
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836 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory
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837 test_dsync(); numtests++;
2
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838 #endif
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839 #ifdef HAL_DCACHE_STORE
143
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840 test_dstore(); numtests++;
2
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841 #endif
583
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diff changeset
842 #ifdef _TEST_DCACHE_OPERATION
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diff changeset
843 test_dcache_operation(); numtests++;
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diff changeset
844 #endif
2
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845 #ifdef HAL_DCACHE_READ_HINT
143
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846 test_dread_hint(); numtests++;
2
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847 #endif
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848 #ifdef HAL_DCACHE_WRITE_HINT
143
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849 test_dwrite_hint(); numtests++;
2
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diff changeset
850 #endif
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851 #ifdef HAL_DCACHE_ZERO
143
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diff changeset
852 test_dzero(); numtests++;
2
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853 #endif
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854
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855 // The below tests only work on a copy-back cache.
24
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diff changeset
856 #ifdef HAL_DCACHE_QUERY_WRITE_MODE
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diff changeset
857 HAL_DCACHE_QUERY_WRITE_MODE( wmode );
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diff changeset
858
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859 if ( HAL_DCACHE_WRITEBACK_MODE == wmode ) {
143
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diff changeset
860 test_ddisable(); numtests++;
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diff changeset
861 #ifdef HAL_DCACHE_INVALIDATE
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diff changeset
862 test_dinvalidate_all(); numtests++;
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diff changeset
863 #endif
2
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864 #ifdef HAL_DCACHE_FLUSH
143
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diff changeset
865 test_dflush(); numtests++;
2
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diff changeset
866 #endif
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867 #ifdef HAL_DCACHE_INVALIDATE
143
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diff changeset
868 test_dinvalidate(); numtests++;
2
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diff changeset
869 #endif
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870 }
24
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diff changeset
871 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
143
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diff changeset
872 if ( numtests ) {
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diff changeset
873 CYG_TEST_PASS_FINISH("End of test");
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diff changeset
874 }
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diff changeset
875 else {
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diff changeset
876 CYG_TEST_NA( "No applicable cache tests" );
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diff changeset
877 }
2
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diff changeset
878 }
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diff changeset
879
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diff changeset
880 // -------------------------------------------------------------------------
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diff changeset
881
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diff changeset
882 void kcache2_main( void )
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883 {
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diff changeset
884 CYG_TEST_INIT();
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diff changeset
885
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diff changeset
886 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache2",
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diff changeset
887 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
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diff changeset
888 cyg_thread_resume(thread[0]);
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diff changeset
889
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diff changeset
890 cyg_scheduler_start();
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diff changeset
891 }
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diff changeset
892
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diff changeset
893 // -------------------------------------------------------------------------
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diff changeset
894
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parents:
diff changeset
895 externC void
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diff changeset
896 cyg_start( void )
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diff changeset
897 {
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diff changeset
898 kcache2_main();
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diff changeset
899 }
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diff changeset
900
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diff changeset
901 // -------------------------------------------------------------------------
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diff changeset
902
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diff changeset
903 #else // def CYGFUN_KERNEL_API_C
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diff changeset
904 #define N_A_MSG "Kernel C API layer disabled"
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905 #endif // def CYGFUN_KERNEL_API_C
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906 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK
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907 #define N_A_MSG "Kernel real-time clock disabled"
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908 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK
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diff changeset
909
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910 #ifdef N_A_MSG
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911 externC void
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912 cyg_start( void )
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913 {
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914 CYG_TEST_INIT();
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915 CYG_TEST_NA( N_A_MSG );
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916 }
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917 #endif // N_A_MSG
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918
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919 // -------------------------------------------------------------------------
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920 /* EOF kcache2.c */