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comparison packages/hal/arm/sa11x0/var/current/include/hal_mm.h @ 145:2e9a636d9de9 ecos-sw-2000-12-21

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Merge from eCos master repository on 2000-12-21-14:18:40-GMT
author jlarmour
date Fri, 22 Dec 2000 02:37:28 +0000
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children 8f2f7615e727
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144:da1052144c56 145:2e9a636d9de9
1 #ifndef CYGONCE_HAL_MM_H
2 #define CYGONCE_HAL_MM_H
3
4 //=============================================================================
5 //
6 // hal_mm.h
7 //
8 // ARM SA11x0 MM common definitions
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 //=============================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): gthomas
38 // Contributors: hmt
39 // Travis C. Furrer <furrer@mit.edu>
40 // Date: 2000-12-13
41 // Purpose: ARM SA11x0 MM common definitions
42 // Description: The macros defined here provide common definitions for
43 // memory management initialization.
44 // Usage:
45 // #include <cyg/hal/hal_mm.h>
46 // ...
47 //
48 //
49 //####DESCRIPTIONEND####
50 //
51 //=============================================================================
52
53
54 // -------------------------------------------------------------------------
55 // MMU initialization:
56 //
57 // These structures are laid down in memory to define the translation
58 // table.
59 //
60
61 /*
62 * SA-1100 Translation Table Base Bit Masks
63 */
64 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
65
66 /*
67 * SA-1100 Domain Access Control Bit Masks
68 */
69 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
70 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
71 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
72
73 struct ARM_MMU_FIRST_LEVEL_FAULT {
74 int id : 2;
75 int sbz : 30;
76 };
77 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
78
79 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
80 int id : 2;
81 int imp : 2;
82 int domain : 4;
83 int sbz : 1;
84 int base_address : 23;
85 };
86 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
87
88 struct ARM_MMU_FIRST_LEVEL_SECTION {
89 int id : 2;
90 int b : 1;
91 int c : 1;
92 int imp : 1;
93 int domain : 4;
94 int sbz0 : 1;
95 int ap : 2;
96 int sbz1 : 8;
97 int base_address : 12;
98 };
99 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
100
101 struct ARM_MMU_FIRST_LEVEL_RESERVED {
102 int id : 2;
103 int sbz : 30;
104 };
105 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
106
107 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
108 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
109
110 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
111
112 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
113 cacheable, bufferable, perm) \
114 CYG_MACRO_START \
115 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
116 \
117 desc.word = 0; \
118 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
119 desc.section.domain = 0; \
120 desc.section.c = (cacheable); \
121 desc.section.b = (bufferable); \
122 desc.section.ap = (perm); \
123 desc.section.base_address = (actual_base); \
124 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
125 = desc.word; \
126 CYG_MACRO_END
127
128 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
129 { int i; int j = abase; int k = vbase; \
130 for (i = size; i > 0 ; i--,j++,k++) \
131 { \
132 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
133 } \
134 }
135
136 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
137 unsigned long word;
138 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
139 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
140 struct ARM_MMU_FIRST_LEVEL_SECTION section;
141 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
142 };
143
144 #define ARM_UNCACHEABLE 0
145 #define ARM_CACHEABLE 1
146 #define ARM_UNBUFFERABLE 0
147 #define ARM_BUFFERABLE 1
148
149 #define ARM_ACCESS_PERM_NONE_NONE 0
150 #define ARM_ACCESS_PERM_RO_NONE 0
151 #define ARM_ACCESS_PERM_RO_RO 0
152 #define ARM_ACCESS_PERM_RW_NONE 1
153 #define ARM_ACCESS_PERM_RW_RO 2
154 #define ARM_ACCESS_PERM_RW_RW 3
155
156 /*
157 * Initialization for the Domain Access Control Register
158 */
159 #define ARM_ACCESS_DACR_DEFAULT ( \
160 ARM_ACCESS_TYPE_MANAGER(0) | \
161 ARM_ACCESS_TYPE_NO_ACCESS(1) | \
162 ARM_ACCESS_TYPE_NO_ACCESS(2) | \
163 ARM_ACCESS_TYPE_NO_ACCESS(3) | \
164 ARM_ACCESS_TYPE_NO_ACCESS(4) | \
165 ARM_ACCESS_TYPE_NO_ACCESS(5) | \
166 ARM_ACCESS_TYPE_NO_ACCESS(6) | \
167 ARM_ACCESS_TYPE_NO_ACCESS(7) | \
168 ARM_ACCESS_TYPE_NO_ACCESS(8) | \
169 ARM_ACCESS_TYPE_NO_ACCESS(9) | \
170 ARM_ACCESS_TYPE_NO_ACCESS(10) | \
171 ARM_ACCESS_TYPE_NO_ACCESS(11) | \
172 ARM_ACCESS_TYPE_NO_ACCESS(12) | \
173 ARM_ACCESS_TYPE_NO_ACCESS(13) | \
174 ARM_ACCESS_TYPE_NO_ACCESS(14) | \
175 ARM_ACCESS_TYPE_NO_ACCESS(15) )
176
177 // ------------------------------------------------------------------------
178 #endif // ifndef CYGONCE_HAL_MM_H
179 // End of hal_mm.h
180
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