Mercurial > flash_v2

annotate packages/hal/arm/sa11x0/var/current/include/hal_mm.h @ 145:2e9a636d9de9 ecos-sw-2000-12-21

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Merge from eCos master repository on 2000-12-21-14:18:40-GMT
author jlarmour
date Fri, 22 Dec 2000 02:37:28 +0000
parents
children 8f2f7615e727
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1 #ifndef CYGONCE_HAL_MM_H
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2 #define CYGONCE_HAL_MM_H
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3
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4 //=============================================================================
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5 //
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6 // hal_mm.h
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7 //
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8 // ARM SA11x0 MM common definitions
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): gthomas
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38 // Contributors: hmt
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39 // Travis C. Furrer <furrer@mit.edu>
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40 // Date: 2000-12-13
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41 // Purpose: ARM SA11x0 MM common definitions
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42 // Description: The macros defined here provide common definitions for
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43 // memory management initialization.
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44 // Usage:
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45 // #include <cyg/hal/hal_mm.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //=============================================================================
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52
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53
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54 // -------------------------------------------------------------------------
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55 // MMU initialization:
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56 //
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57 // These structures are laid down in memory to define the translation
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58 // table.
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59 //
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60
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61 /*
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62 * SA-1100 Translation Table Base Bit Masks
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63 */
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64 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
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65
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66 /*
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67 * SA-1100 Domain Access Control Bit Masks
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68 */
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69 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
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70 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
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71 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
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72
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73 struct ARM_MMU_FIRST_LEVEL_FAULT {
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74 int id : 2;
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75 int sbz : 30;
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76 };
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77 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
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78
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79 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
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80 int id : 2;
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81 int imp : 2;
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82 int domain : 4;
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83 int sbz : 1;
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84 int base_address : 23;
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85 };
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86 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
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87
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88 struct ARM_MMU_FIRST_LEVEL_SECTION {
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89 int id : 2;
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90 int b : 1;
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91 int c : 1;
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92 int imp : 1;
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93 int domain : 4;
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94 int sbz0 : 1;
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95 int ap : 2;
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96 int sbz1 : 8;
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97 int base_address : 12;
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98 };
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99 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
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100
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101 struct ARM_MMU_FIRST_LEVEL_RESERVED {
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102 int id : 2;
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103 int sbz : 30;
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104 };
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105 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
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106
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107 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
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108 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
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109
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110 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
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111
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112 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
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113 cacheable, bufferable, perm) \
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114 CYG_MACRO_START \
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115 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
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116 \
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117 desc.word = 0; \
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118 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
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119 desc.section.domain = 0; \
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120 desc.section.c = (cacheable); \
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121 desc.section.b = (bufferable); \
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122 desc.section.ap = (perm); \
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123 desc.section.base_address = (actual_base); \
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124 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
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125 = desc.word; \
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126 CYG_MACRO_END
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127
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128 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
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129 { int i; int j = abase; int k = vbase; \
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130 for (i = size; i > 0 ; i--,j++,k++) \
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131 { \
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132 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
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133 } \
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134 }
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135
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136 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
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137 unsigned long word;
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138 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
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139 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
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140 struct ARM_MMU_FIRST_LEVEL_SECTION section;
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141 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
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142 };
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143
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144 #define ARM_UNCACHEABLE 0
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145 #define ARM_CACHEABLE 1
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146 #define ARM_UNBUFFERABLE 0
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147 #define ARM_BUFFERABLE 1
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148
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149 #define ARM_ACCESS_PERM_NONE_NONE 0
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150 #define ARM_ACCESS_PERM_RO_NONE 0
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151 #define ARM_ACCESS_PERM_RO_RO 0
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152 #define ARM_ACCESS_PERM_RW_NONE 1
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153 #define ARM_ACCESS_PERM_RW_RO 2
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154 #define ARM_ACCESS_PERM_RW_RW 3
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155
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156 /*
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157 * Initialization for the Domain Access Control Register
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158 */
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159 #define ARM_ACCESS_DACR_DEFAULT ( \
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160 ARM_ACCESS_TYPE_MANAGER(0) | \
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161 ARM_ACCESS_TYPE_NO_ACCESS(1) | \
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162 ARM_ACCESS_TYPE_NO_ACCESS(2) | \
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163 ARM_ACCESS_TYPE_NO_ACCESS(3) | \
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164 ARM_ACCESS_TYPE_NO_ACCESS(4) | \
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165 ARM_ACCESS_TYPE_NO_ACCESS(5) | \
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166 ARM_ACCESS_TYPE_NO_ACCESS(6) | \
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167 ARM_ACCESS_TYPE_NO_ACCESS(7) | \
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168 ARM_ACCESS_TYPE_NO_ACCESS(8) | \
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169 ARM_ACCESS_TYPE_NO_ACCESS(9) | \
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170 ARM_ACCESS_TYPE_NO_ACCESS(10) | \
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171 ARM_ACCESS_TYPE_NO_ACCESS(11) | \
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172 ARM_ACCESS_TYPE_NO_ACCESS(12) | \
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173 ARM_ACCESS_TYPE_NO_ACCESS(13) | \
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174 ARM_ACCESS_TYPE_NO_ACCESS(14) | \
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175 ARM_ACCESS_TYPE_NO_ACCESS(15) )
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176
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177 // ------------------------------------------------------------------------
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178 #endif // ifndef CYGONCE_HAL_MM_H
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179 // End of hal_mm.h
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180
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181
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182
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183
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184