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comparison packages/hal/powerpc/sim/current/src/sim.ld @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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-1:000000000000 0:3111d98ba7b3
1 //==========================================================================
2 //
3 // sim.ld
4 //
5 // Linker script for PowerPC simulator
6 //
7 //==========================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Cygnus Public License
12 // Version 1.0 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.cygnus.com.
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos code, released September 30, 1998.
22 //
23 // The Initial Developer of the Original Code is Cygnus. Portions created
24 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
25 // -------------------------------------------
26 //
27 //####COPYRIGHTEND####
28 //==========================================================================
29 //#####DESCRIPTIONBEGIN####
30 //
31 // Author(s): nickg
32 // Contributors:nickg
33 // Date: 1998-02-17
34 // Purpose: PowerPC simulator Linker script
35 // Description: This script is passed to the linker to define the memory
36 // of the PowerPC simulator.
37 //
38 //####DESCRIPTIONEND####
39 //
40 //==========================================================================
41 STARTUP(vectors.o)
42 OUTPUT_FORMAT("elf32-powerpc")
43 OUTPUT_ARCH(powerpc)
44 ENTRY(reset_vector)
45 // Do we need any of these for elf?
46 // __DYNAMIC = 0;
47
48 GROUP(libtarget.a libgcc.a)
49
50 #include <pkgconf/hal.h>
51
52 MEMORY
53 {
54
55 // In a RAM system, fake the division between ROM and
56 // RAM for testing.
57 ram_vectors : ORIGIN = 0x00000000, LENGTH = 0x2000
58 rom_vectors : ORIGIN = 0x00002000, LENGTH = 0x2000
59 ram : ORIGIN = 0x00004000, LENGTH = 496k
60 rom : ORIGIN = 0x00080000, LENGTH = 512k
61 }
62
63 // Allocate the stack to be at the top of memory, since the stack
64 // grows down
65
66 PROVIDE (__interrupt_stack = 0x00100000);
67
68 // Initalize some symbols to be zero so we can reference them in the
69 // crt0 without core dumping. These functions are all optional, but
70 // we do this so we can have our crt0 always use them if they exist.
71 // This is so BSPs work better when using the crt0 installed gcc.
72 // We have to initalize them twice, so we cover a.out (which prepends
73 // an underscore) and coff object file formats.
74
75 //PROVIDE (hardware_init_hook = 0);
76 //PROVIDE (software_init_hook = 0);
77
78 SECTIONS
79 {
80 // Read-only sections, merged into text segment:
81 .interp : { *(.interp) } >rom
82 .hash : { *(.hash) } >rom
83 .dynsym : { *(.dynsym) } >rom
84 .dynstr : { *(.dynstr) } >rom
85 .rel.text : { *(.rel.text) } >rom
86 .rela.text : { *(.rela.text) } >rom
87 .rel.data : { *(.rel.data) } >rom
88 .rela.data : { *(.rela.data) } >rom
89 .rel.rodata : { *(.rel.rodata) } >rom
90 .rela.rodata : { *(.rela.rodata) } >rom
91 .rel.got : { *(.rel.got) } >rom
92 .rela.got : { *(.rela.got) } >rom
93 .rel.got1 : { *(.rel.got1) } >rom
94 .rela.got1 : { *(.rela.got1) } >rom
95 .rel.got2 : { *(.rel.got2) } >rom
96 .rela.got2 : { *(.rela.got2) } >rom
97 .rel.ctors : { *(.rel.ctors) } >rom
98 .rela.ctors : { *(.rela.ctors) } >rom
99 .rel.dtors : { *(.rel.dtors) } >rom
100 .rela.dtors : { *(.rela.dtors) } >rom
101 .rel.init : { *(.rel.init) } >rom
102 .rela.init : { *(.rela.init) } >rom
103 .rel.fini : { *(.rel.fini) } >rom
104 .rela.fini : { *(.rela.fini) } >rom
105 .rel.bss : { *(.rel.bss) } >rom
106 .rela.bss : { *(.rela.bss) } >rom
107 .rel.plt : { *(.rel.plt) } >rom
108 .rela.plt : { *(.rela.plt) } >rom
109 .init : {
110 *(.init.head)
111 *(.init)
112 *(.init.tail)
113 } >rom =0
114 .plt : { *(.plt) } >rom
115 .text :
116 {
117 _stext = .;
118 *(.text*)
119 *(.gnu.warning)
120 *(.gnu.linkonce*)
121 } >rom =0
122 _etext = .;
123 PROVIDE (etext = .);
124 .fini : {
125 *(.fini.head)
126 *(.fini)
127 *(.fini.tail)
128 } >rom =0
129
130 .rodata1 : { *(.rodata1) } >rom
131 .rodata : { *(.rodata*) } >rom
132 __FIXUP_START__ = .;
133 .fixup : { *(.fixup) } >rom
134 __FIXUP_END__ = .;
135 __EXCEPT_START__ =.;
136 .gcc_except_table : { *(.gcc_except_table) } >rom
137 __EXCEPT_END__ =.;
138 // Read-write section, merged into data segment:
139 __rom_data_start = ALIGN(4);
140 .data :
141 AT( __rom_data_start )
142 {
143 __ram_data_start = .;
144 PROVIDE( __ram_data_start = .);
145
146 *(.data*)
147 __GOT1_START__ = .;
148 *(.got1)
149 __GOT1_END__ = .;
150 // Put .ctors and .dtors next to the .got2 section, so that the pointers
151 // get relocated with -mrelocatable.
152 #ifdef CYG_KERNEL_USE_INIT_PRIORITY
153 . = ALIGN(8);
154 __CTOR_LIST__ = .;
155 KEEP(*(SORT(.ctors*)))
156 __CTOR_END__ = .;
157 __DTOR_LIST__ = .;
158 KEEP(*(SORT(.dtors*)))
159 __DTOR_END__ = .;
160 #else
161 __CTOR_LIST__ = .;
162 *sched.o(.ctors*)
163 *clock.o(.ctors*)
164 *thread.o(.ctors*)
165 *(.ctors*)
166 __CTOR_END__ = .;
167 __DTOR_LIST__ = .;
168 *(.dtors*)
169 __DTOR_END__ = .;
170 #endif
171 __GOT2_START__ = .;
172 *(.got2)
173 __GOT2_END__ = .;
174 __GOT_START__ = .;
175 _GLOBAL_OFFSET_TABLE_ = . + 32768;
176 _SDA_BASE_ = .;
177 *(.got.plt)
178 *(.got)
179 __GOT_END__ = .;
180 *(.dynamic)
181 // We want the small data sections together, so single-instruction offsets
182 // can access them all, and initialized data all before uninitialized, so
183 // we can shorten the on-disk segment size.
184 __SDATA_START__ = .;
185 *(.sdata)
186 __SDATA2_START__ = .;
187 *(.sdata2)
188 } >ram
189 __ram_data_end = .;
190 PROVIDE( __ram_data_end = .);
191 _edata = .;
192 PROVIDE (edata = .);
193 __bss_start = .;
194 .sbss :
195 {
196 __SBSS_START__ = .;
197 *(.sbss*)
198 __SBSS_END__ = .;
199 __SBSS2_START__ = .;
200 *(.sbss2)
201 __SBSS2_END__ = .;
202 *(.scommon)
203 } >ram
204
205 .bss :
206 {
207 *(.dynbss)
208 *(.bss)
209 *(COMMON)
210 } >ram
211 _end = . ;
212 PROVIDE (end = .);
213
214
215 __rom_ram_vectors_start = ALIGN(4);
216 #if 1
217 .vectors :
218 {
219 *(.vectors)
220 } > ram_vectors
221 #else
222 .ram_vectors :
223 AT ( __rom_ram_vectors_start )
224 {
225 __ram_vectors_start = .;
226 *(.ram_vectors)
227 __ram_vectors_end = .;
228 } >ram_vectors
229
230 .rom_vectors :
231 {
232 *(.rom_vectors)
233 } >rom_vectors
234 #endif
235
236 }
237