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1 //========================================================================== |
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2 // |
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3 // sim.ld |
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4 // |
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5 // Linker script for PowerPC simulator |
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6 // |
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7 //========================================================================== |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Cygnus Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://www.cygnus.com. |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos code, released September 30, 1998. |
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22 // |
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23 // The Initial Developer of the Original Code is Cygnus. Portions created |
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24 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
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25 // ------------------------------------------- |
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26 // |
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27 //####COPYRIGHTEND#### |
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28 //========================================================================== |
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29 //#####DESCRIPTIONBEGIN#### |
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30 // |
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31 // Author(s): nickg |
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32 // Contributors:nickg |
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33 // Date: 1998-02-17 |
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34 // Purpose: PowerPC simulator Linker script |
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35 // Description: This script is passed to the linker to define the memory |
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36 // of the PowerPC simulator. |
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37 // |
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38 //####DESCRIPTIONEND#### |
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39 // |
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40 //========================================================================== |
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41 STARTUP(vectors.o) |
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42 OUTPUT_FORMAT("elf32-powerpc") |
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43 OUTPUT_ARCH(powerpc) |
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44 ENTRY(reset_vector) |
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45 // Do we need any of these for elf? |
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46 // __DYNAMIC = 0; |
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47 |
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48 GROUP(libtarget.a libgcc.a) |
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49 |
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50 #include <pkgconf/hal.h> |
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51 |
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52 MEMORY |
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53 { |
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54 |
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55 // In a RAM system, fake the division between ROM and |
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56 // RAM for testing. |
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57 ram_vectors : ORIGIN = 0x00000000, LENGTH = 0x2000 |
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58 rom_vectors : ORIGIN = 0x00002000, LENGTH = 0x2000 |
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59 ram : ORIGIN = 0x00004000, LENGTH = 496k |
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60 rom : ORIGIN = 0x00080000, LENGTH = 512k |
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61 } |
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62 |
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63 // Allocate the stack to be at the top of memory, since the stack |
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64 // grows down |
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65 |
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66 PROVIDE (__interrupt_stack = 0x00100000); |
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67 |
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68 // Initalize some symbols to be zero so we can reference them in the |
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69 // crt0 without core dumping. These functions are all optional, but |
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70 // we do this so we can have our crt0 always use them if they exist. |
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71 // This is so BSPs work better when using the crt0 installed gcc. |
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72 // We have to initalize them twice, so we cover a.out (which prepends |
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73 // an underscore) and coff object file formats. |
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74 |
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75 //PROVIDE (hardware_init_hook = 0); |
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76 //PROVIDE (software_init_hook = 0); |
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77 |
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78 SECTIONS |
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79 { |
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80 // Read-only sections, merged into text segment: |
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81 .interp : { *(.interp) } >rom |
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82 .hash : { *(.hash) } >rom |
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83 .dynsym : { *(.dynsym) } >rom |
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84 .dynstr : { *(.dynstr) } >rom |
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85 .rel.text : { *(.rel.text) } >rom |
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86 .rela.text : { *(.rela.text) } >rom |
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87 .rel.data : { *(.rel.data) } >rom |
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88 .rela.data : { *(.rela.data) } >rom |
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89 .rel.rodata : { *(.rel.rodata) } >rom |
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90 .rela.rodata : { *(.rela.rodata) } >rom |
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91 .rel.got : { *(.rel.got) } >rom |
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92 .rela.got : { *(.rela.got) } >rom |
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93 .rel.got1 : { *(.rel.got1) } >rom |
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94 .rela.got1 : { *(.rela.got1) } >rom |
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95 .rel.got2 : { *(.rel.got2) } >rom |
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96 .rela.got2 : { *(.rela.got2) } >rom |
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97 .rel.ctors : { *(.rel.ctors) } >rom |
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98 .rela.ctors : { *(.rela.ctors) } >rom |
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99 .rel.dtors : { *(.rel.dtors) } >rom |
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100 .rela.dtors : { *(.rela.dtors) } >rom |
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101 .rel.init : { *(.rel.init) } >rom |
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102 .rela.init : { *(.rela.init) } >rom |
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103 .rel.fini : { *(.rel.fini) } >rom |
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104 .rela.fini : { *(.rela.fini) } >rom |
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105 .rel.bss : { *(.rel.bss) } >rom |
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106 .rela.bss : { *(.rela.bss) } >rom |
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107 .rel.plt : { *(.rel.plt) } >rom |
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108 .rela.plt : { *(.rela.plt) } >rom |
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109 .init : { |
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110 *(.init.head) |
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111 *(.init) |
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112 *(.init.tail) |
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113 } >rom =0 |
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114 .plt : { *(.plt) } >rom |
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115 .text : |
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116 { |
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117 _stext = .; |
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118 *(.text*) |
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119 *(.gnu.warning) |
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120 *(.gnu.linkonce*) |
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121 } >rom =0 |
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122 _etext = .; |
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123 PROVIDE (etext = .); |
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124 .fini : { |
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125 *(.fini.head) |
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126 *(.fini) |
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127 *(.fini.tail) |
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128 } >rom =0 |
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129 |
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130 .rodata1 : { *(.rodata1) } >rom |
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131 .rodata : { *(.rodata*) } >rom |
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132 __FIXUP_START__ = .; |
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133 .fixup : { *(.fixup) } >rom |
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134 __FIXUP_END__ = .; |
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135 __EXCEPT_START__ =.; |
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136 .gcc_except_table : { *(.gcc_except_table) } >rom |
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137 __EXCEPT_END__ =.; |
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138 // Read-write section, merged into data segment: |
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139 __rom_data_start = ALIGN(4); |
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140 .data : |
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141 AT( __rom_data_start ) |
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142 { |
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143 __ram_data_start = .; |
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144 PROVIDE( __ram_data_start = .); |
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145 |
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146 *(.data*) |
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147 __GOT1_START__ = .; |
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148 *(.got1) |
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149 __GOT1_END__ = .; |
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150 // Put .ctors and .dtors next to the .got2 section, so that the pointers |
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151 // get relocated with -mrelocatable. |
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152 #ifdef CYG_KERNEL_USE_INIT_PRIORITY |
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153 . = ALIGN(8); |
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154 __CTOR_LIST__ = .; |
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155 KEEP(*(SORT(.ctors*))) |
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156 __CTOR_END__ = .; |
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157 __DTOR_LIST__ = .; |
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158 KEEP(*(SORT(.dtors*))) |
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159 __DTOR_END__ = .; |
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160 #else |
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161 __CTOR_LIST__ = .; |
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162 *sched.o(.ctors*) |
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163 *clock.o(.ctors*) |
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164 *thread.o(.ctors*) |
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165 *(.ctors*) |
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166 __CTOR_END__ = .; |
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167 __DTOR_LIST__ = .; |
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168 *(.dtors*) |
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169 __DTOR_END__ = .; |
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170 #endif |
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171 __GOT2_START__ = .; |
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172 *(.got2) |
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173 __GOT2_END__ = .; |
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174 __GOT_START__ = .; |
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175 _GLOBAL_OFFSET_TABLE_ = . + 32768; |
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176 _SDA_BASE_ = .; |
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177 *(.got.plt) |
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178 *(.got) |
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179 __GOT_END__ = .; |
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180 *(.dynamic) |
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181 // We want the small data sections together, so single-instruction offsets |
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182 // can access them all, and initialized data all before uninitialized, so |
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183 // we can shorten the on-disk segment size. |
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184 __SDATA_START__ = .; |
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185 *(.sdata) |
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186 __SDATA2_START__ = .; |
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187 *(.sdata2) |
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188 } >ram |
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189 __ram_data_end = .; |
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190 PROVIDE( __ram_data_end = .); |
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191 _edata = .; |
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192 PROVIDE (edata = .); |
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193 __bss_start = .; |
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194 .sbss : |
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195 { |
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196 __SBSS_START__ = .; |
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197 *(.sbss*) |
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198 __SBSS_END__ = .; |
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199 __SBSS2_START__ = .; |
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200 *(.sbss2) |
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201 __SBSS2_END__ = .; |
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202 *(.scommon) |
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203 } >ram |
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204 |
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205 .bss : |
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206 { |
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207 *(.dynbss) |
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208 *(.bss) |
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209 *(COMMON) |
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210 } >ram |
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211 _end = . ; |
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212 PROVIDE (end = .); |
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213 |
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214 |
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215 __rom_ram_vectors_start = ALIGN(4); |
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216 #if 1 |
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217 .vectors : |
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218 { |
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219 *(.vectors) |
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220 } > ram_vectors |
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221 #else |
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222 .ram_vectors : |
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223 AT ( __rom_ram_vectors_start ) |
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224 { |
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225 __ram_vectors_start = .; |
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226 *(.ram_vectors) |
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227 __ram_vectors_end = .; |
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228 } >ram_vectors |
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229 |
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230 .rom_vectors : |
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231 { |
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232 *(.rom_vectors) |
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233 } >rom_vectors |
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234 #endif |
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235 |
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236 } |
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237 |
