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comparison packages/hal/mips/vrc4373/current/include/plf_intr.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 25e238959bae
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75:41bf073c0c32 76:435cced73e2f
1 #ifndef CYGONCE_HAL_PLF_INTR_H
2 #define CYGONCE_HAL_PLF_INTR_H
3
4 //==========================================================================
5 //
6 // plf_intr.h
7 //
8 // VRC4373 Interrupt and clock support
9 //
10 //==========================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 //==========================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): nickg
38 // Contributors: nickg, jskov,
39 // gthomas, jlarmour
40 // Date: 1999-02-16
41 // Purpose: Define Interrupt support
42 // Description: The macros defined here provide the HAL APIs for handling
43 // interrupts and the clock for the VRC4373 board.
44 //
45 // Usage:
46 // #include <cyg/hal/plf_intr.h>
47 // ...
48 //
49 //
50 //####DESCRIPTIONEND####
51 //
52 //==========================================================================
53
54 #include <pkgconf/hal.h>
55
56 #include <cyg/infra/cyg_type.h>
57
58 //--------------------------------------------------------------------------
59 // Interrupt controller stuff.
60
61 // The first 6 correspond to the interrupt lines in the status/cause regs
62 #define CYGNUM_HAL_INTERRUPT_VRC4373 0
63 #define CYGNUM_HAL_INTERRUPT_IPL0 1
64 #define CYGNUM_HAL_INTERRUPT_IPL1 2
65 #define CYGNUM_HAL_INTERRUPT_IPL2 3
66 #define CYGNUM_HAL_INTERRUPT_POWER 4
67 #define CYGNUM_HAL_INTERRUPT_COMPARE 5
68 // The next 32 correspond to the interrupt lines in the 4372 interrupt
69 // controller. These are decoded from the controller when an interrupt
70 // on any of the IPL[0:2] lines in signalled.
71 #define CYGNUM_HAL_INTERRUPT_REALTIME_A 6
72 #define CYGNUM_HAL_INTERRUPT_REALTIME_B 7
73 #define CYGNUM_HAL_INTERRUPT_DUART 8
74 #define CYGNUM_HAL_INTERRUPT_TIMER 9
75 #define CYGNUM_HAL_INTERRUPT_PARALLEL 10
76 #define CYGNUM_HAL_INTERRUPT_PCI_INTA 11
77 #define CYGNUM_HAL_INTERRUPT_PCI_INTB 12
78 #define CYGNUM_HAL_INTERRUPT_PCI_INTC 13
79 #define CYGNUM_HAL_INTERRUPT_PCI_INTD 14
80 #define CYGNUM_HAL_INTERRUPT_INT_9 15
81 #define CYGNUM_HAL_INTERRUPT_INT_10 16
82 #define CYGNUM_HAL_INTERRUPT_INT_11 17
83 #define CYGNUM_HAL_INTERRUPT_INT_12 18
84 #define CYGNUM_HAL_INTERRUPT_INT_13 19
85 #define CYGNUM_HAL_INTERRUPT_DMA_0 20
86 #define CYGNUM_HAL_INTERRUPT_DMA_1 21
87 #define CYGNUM_HAL_INTERRUPT_DMA_2 22
88 #define CYGNUM_HAL_INTERRUPT_DMA_3 23
89 #define CYGNUM_HAL_INTERRUPT_TICK_0 24
90 #define CYGNUM_HAL_INTERRUPT_TICK_1 25
91 #define CYGNUM_HAL_INTERRUPT_UNUSED_20 26
92 #define CYGNUM_HAL_INTERRUPT_UNUSED_21 27
93 #define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28
94 #define CYGNUM_HAL_INTERRUPT_PCI_PERR 29
95 #define CYGNUM_HAL_INTERRUPT_PCI_SERR 30
96 #define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31
97 #define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32
98 #define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33
99 #define CYGNUM_HAL_INTERRUPT_PCI_ADD 34
100 #define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35
101 #define CYGNUM_HAL_INTERRUPT_UNUSED_30 36
102 #define CYGNUM_HAL_INTERRUPT_UNUSED_31 37
103
104 // Min/Max ISR numbers and how many there are
105 #define CYGNUM_HAL_ISR_MIN 0
106 #define CYGNUM_HAL_ISR_MAX 37
107 #define CYGNUM_HAL_ISR_COUNT 38
108
109 // The vector used by the Real time clock. The default here is to use
110 // interrupt 5, which is connected to the counter/comparator registers
111 // in many MIPS variants.
112
113 #ifndef CYGNUM_HAL_INTERRUPT_RTC
114 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
115 #endif
116
117 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
118
119 //--------------------------------------------------------------------------
120 // controller access code
121
122 #define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000
123 #define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200)
124 #define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204)
125 #define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208)
126 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c)
127 #define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210)
128 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214)
129 #define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218)
130 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c)
131 #define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220)
132
133 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF 8
134
135 // Array which stores the configured priority levels for the configured
136 // interrupts.
137 externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
138
139 #define HAL_INTERRUPT_MASK( _vector_ ) \
140 CYG_MACRO_START \
141 if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
142 { \
143 asm volatile ( \
144 "mfc0 $3,$12\n" \
145 "la $2,0x00000400\n" \
146 "sllv $2,$2,%0\n" \
147 "nor $2,$2,$0\n" \
148 "and $3,$3,$2\n" \
149 "mtc0 $3,$12\n" \
150 "nop; nop; nop\n" \
151 : \
152 : "r"(_vector_) \
153 : "$2", "$3" \
154 ); \
155 } \
156 else \
157 { \
158 CYG_WORD32 _mask_; \
159 CYG_BYTE _shift_; \
160 HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + \
161 cyg_hal_interrupt_level[_vector_] * \
162 CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \
163 HAL_READ_UINT32( _maskreg_, _mask_ ); \
164 _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
165 _mask_ &= ~(1<<_shift_); \
166 HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
167 } \
168 CYG_MACRO_END
169
170 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
171 CYG_MACRO_START \
172 if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
173 { \
174 asm volatile ( \
175 "mfc0 $3,$12\n" \
176 "la $2,0x00000400\n" \
177 "sllv $2,$2,%0\n" \
178 "or $3,$3,$2\n" \
179 "mtc0 $3,$12\n" \
180 "nop; nop; nop\n" \
181 : \
182 : "r"(_vector_) \
183 : "$2", "$3" \
184 ); \
185 } \
186 else \
187 { \
188 CYG_WORD32 _mask_; \
189 CYG_BYTE _shift_; \
190 HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + \
191 cyg_hal_interrupt_level[_vector_] * \
192 CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \
193 HAL_READ_UINT32( _maskreg_, _mask_ ); \
194 _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
195 _mask_ |= 1<<_shift_; \
196 HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
197 } \
198 CYG_MACRO_END
199
200 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
201 CYG_MACRO_START \
202 CYG_WORD32 _srvector_ = _vector_; \
203 if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
204 { \
205 CYG_WORD32 _stat_; \
206 CYG_BYTE _shift_; \
207 HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 +\
208 cyg_hal_interrupt_level[_vector_] * \
209 CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \
210 HAL_READ_UINT32( _statreg_, _stat_ ); \
211 _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
212 _stat_ &= ~(1<<_shift_); \
213 HAL_WRITE_UINT32( _statreg_, _stat_ ); \
214 _srvector_ = cyg_hal_interrupt_level[_vector_] + \
215 CYGNUM_HAL_INTERRUPT_IPL0; \
216 } \
217 asm volatile ( \
218 "mfc0 $3,$13\n" \
219 "la $2,0x00000400\n" \
220 "sllv $2,$2,%0\n" \
221 "nor $2,$2,$0\n" \
222 "and $3,$3,$2\n" \
223 "mtc0 $3,$13\n" \
224 "nop; nop; nop\n" \
225 : \
226 : "r"(_srvector_) \
227 : "$2", "$3" \
228 ); \
229 CYG_MACRO_END
230
231 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
232 CYG_MACRO_START \
233 if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \
234 (_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \
235 { \
236 CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \
237 CYG_WORD32 pol; \
238 CYG_WORD32 trig; \
239 HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_POL, pol ); \
240 HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG, trig ); \
241 if( _level_ ) \
242 { \
243 pol &= ~mask; \
244 if( _up_ ) trig |= mask; \
245 else trig &= ~mask; \
246 } \
247 else \
248 { \
249 pol |= mask; \
250 if( !(_up_) ) trig |= mask; \
251 else trig &= ~mask; \
252 } \
253 HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_POL, pol ); \
254 HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG, trig ); \
255 } \
256 CYG_MACRO_END
257
258 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
259 CYG_MACRO_START \
260 if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
261 { \
262 cyg_uint32 _ilevel_ = _level_; \
263 while( _ilevel_ > 2 ) _ilevel_ -= 2; \
264 cyg_hal_interrupt_level[_vector_] = _ilevel_; \
265 } \
266 CYG_MACRO_END
267
268 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
269
270 //--------------------------------------------------------------------------
271 // Control-C support.
272
273 #if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
274
275 # define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
276
277 externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
278
279 #define HAL_CTRLC_ISR hal_ctrlc_isr
280
281 #endif
282
283 //--------------------------------------------------------------------------
284 #endif // ifndef CYGONCE_HAL_PLF_INTR_H
285 // End of plf_intr.h