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annotate packages/hal/mips/vrc4373/current/include/plf_intr.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 25e238959bae
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 #ifndef CYGONCE_HAL_PLF_INTR_H
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2 #define CYGONCE_HAL_PLF_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // plf_intr.h
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7 //
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8 // VRC4373 Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg
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38 // Contributors: nickg, jskov,
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39 // gthomas, jlarmour
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40 // Date: 1999-02-16
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41 // Purpose: Define Interrupt support
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42 // Description: The macros defined here provide the HAL APIs for handling
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43 // interrupts and the clock for the VRC4373 board.
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44 //
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45 // Usage:
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46 // #include <cyg/hal/plf_intr.h>
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47 // ...
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48 //
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //==========================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/infra/cyg_type.h>
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57
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58 //--------------------------------------------------------------------------
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59 // Interrupt controller stuff.
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60
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61 // The first 6 correspond to the interrupt lines in the status/cause regs
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62 #define CYGNUM_HAL_INTERRUPT_VRC4373 0
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63 #define CYGNUM_HAL_INTERRUPT_IPL0 1
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64 #define CYGNUM_HAL_INTERRUPT_IPL1 2
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65 #define CYGNUM_HAL_INTERRUPT_IPL2 3
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66 #define CYGNUM_HAL_INTERRUPT_POWER 4
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67 #define CYGNUM_HAL_INTERRUPT_COMPARE 5
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68 // The next 32 correspond to the interrupt lines in the 4372 interrupt
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69 // controller. These are decoded from the controller when an interrupt
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70 // on any of the IPL[0:2] lines in signalled.
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71 #define CYGNUM_HAL_INTERRUPT_REALTIME_A 6
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72 #define CYGNUM_HAL_INTERRUPT_REALTIME_B 7
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73 #define CYGNUM_HAL_INTERRUPT_DUART 8
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74 #define CYGNUM_HAL_INTERRUPT_TIMER 9
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75 #define CYGNUM_HAL_INTERRUPT_PARALLEL 10
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76 #define CYGNUM_HAL_INTERRUPT_PCI_INTA 11
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77 #define CYGNUM_HAL_INTERRUPT_PCI_INTB 12
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78 #define CYGNUM_HAL_INTERRUPT_PCI_INTC 13
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79 #define CYGNUM_HAL_INTERRUPT_PCI_INTD 14
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80 #define CYGNUM_HAL_INTERRUPT_INT_9 15
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81 #define CYGNUM_HAL_INTERRUPT_INT_10 16
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82 #define CYGNUM_HAL_INTERRUPT_INT_11 17
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83 #define CYGNUM_HAL_INTERRUPT_INT_12 18
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84 #define CYGNUM_HAL_INTERRUPT_INT_13 19
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85 #define CYGNUM_HAL_INTERRUPT_DMA_0 20
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86 #define CYGNUM_HAL_INTERRUPT_DMA_1 21
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87 #define CYGNUM_HAL_INTERRUPT_DMA_2 22
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88 #define CYGNUM_HAL_INTERRUPT_DMA_3 23
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89 #define CYGNUM_HAL_INTERRUPT_TICK_0 24
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90 #define CYGNUM_HAL_INTERRUPT_TICK_1 25
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91 #define CYGNUM_HAL_INTERRUPT_UNUSED_20 26
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92 #define CYGNUM_HAL_INTERRUPT_UNUSED_21 27
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93 #define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28
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94 #define CYGNUM_HAL_INTERRUPT_PCI_PERR 29
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95 #define CYGNUM_HAL_INTERRUPT_PCI_SERR 30
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96 #define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31
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97 #define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32
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98 #define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33
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99 #define CYGNUM_HAL_INTERRUPT_PCI_ADD 34
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100 #define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35
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101 #define CYGNUM_HAL_INTERRUPT_UNUSED_30 36
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102 #define CYGNUM_HAL_INTERRUPT_UNUSED_31 37
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103
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104 // Min/Max ISR numbers and how many there are
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105 #define CYGNUM_HAL_ISR_MIN 0
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106 #define CYGNUM_HAL_ISR_MAX 37
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107 #define CYGNUM_HAL_ISR_COUNT 38
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108
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109 // The vector used by the Real time clock. The default here is to use
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110 // interrupt 5, which is connected to the counter/comparator registers
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111 // in many MIPS variants.
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112
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113 #ifndef CYGNUM_HAL_INTERRUPT_RTC
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114 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
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115 #endif
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116
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117 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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118
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119 //--------------------------------------------------------------------------
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120 // controller access code
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121
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122 #define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000
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123 #define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200)
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124 #define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204)
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125 #define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208)
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126 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c)
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127 #define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210)
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128 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214)
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129 #define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218)
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130 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c)
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131 #define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220)
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132
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133 #define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF 8
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134
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135 // Array which stores the configured priority levels for the configured
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136 // interrupts.
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137 externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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138
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139 #define HAL_INTERRUPT_MASK( _vector_ ) \
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140 CYG_MACRO_START \
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141 if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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142 { \
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143 asm volatile ( \
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144 "mfc0 $3,$12\n" \
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145 "la $2,0x00000400\n" \
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146 "sllv $2,$2,%0\n" \
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147 "nor $2,$2,$0\n" \
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148 "and $3,$3,$2\n" \
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149 "mtc0 $3,$12\n" \
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150 "nop; nop; nop\n" \
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151 : \
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152 : "r"(_vector_) \
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153 : "$2", "$3" \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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154 ); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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155 } \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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156 else \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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157 { \
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158 CYG_WORD32 _mask_; \
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159 CYG_BYTE _shift_; \
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160 HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + \
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161 cyg_hal_interrupt_level[_vector_] * \
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162 CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \
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163 HAL_READ_UINT32( _maskreg_, _mask_ ); \
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164 _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
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165 _mask_ &= ~(1<<_shift_); \
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166 HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
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167 } \
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168 CYG_MACRO_END
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169
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170 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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171 CYG_MACRO_START \
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172 if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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173 { \
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174 asm volatile ( \
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175 "mfc0 $3,$12\n" \
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176 "la $2,0x00000400\n" \
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177 "sllv $2,$2,%0\n" \
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178 "or $3,$3,$2\n" \
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179 "mtc0 $3,$12\n" \
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180 "nop; nop; nop\n" \
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181 : \
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182 : "r"(_vector_) \
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183 : "$2", "$3" \
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184 ); \
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185 } \
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186 else \
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187 { \
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188 CYG_WORD32 _mask_; \
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189 CYG_BYTE _shift_; \
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190 HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + \
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191 cyg_hal_interrupt_level[_vector_] * \
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192 CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \
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193 HAL_READ_UINT32( _maskreg_, _mask_ ); \
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194 _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
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195 _mask_ |= 1<<_shift_; \
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196 HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
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197 } \
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198 CYG_MACRO_END
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199
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200 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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201 CYG_MACRO_START \
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202 CYG_WORD32 _srvector_ = _vector_; \
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203 if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
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204 { \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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205 CYG_WORD32 _stat_; \
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206 CYG_BYTE _shift_; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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207 HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 +\
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208 cyg_hal_interrupt_level[_vector_] * \
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209 CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \
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210 HAL_READ_UINT32( _statreg_, _stat_ ); \
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211 _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
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212 _stat_ &= ~(1<<_shift_); \
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213 HAL_WRITE_UINT32( _statreg_, _stat_ ); \
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214 _srvector_ = cyg_hal_interrupt_level[_vector_] + \
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215 CYGNUM_HAL_INTERRUPT_IPL0; \
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216 } \
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217 asm volatile ( \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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218 "mfc0 $3,$13\n" \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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219 "la $2,0x00000400\n" \
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220 "sllv $2,$2,%0\n" \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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221 "nor $2,$2,$0\n" \
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222 "and $3,$3,$2\n" \
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223 "mtc0 $3,$13\n" \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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224 "nop; nop; nop\n" \
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225 : \
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226 : "r"(_srvector_) \
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227 : "$2", "$3" \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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228 ); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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229 CYG_MACRO_END
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230
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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231 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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232 CYG_MACRO_START \
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233 if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \
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234 (_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \
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235 { \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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236 CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \
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237 CYG_WORD32 pol; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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238 CYG_WORD32 trig; \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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239 HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_POL, pol ); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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240 HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG, trig ); \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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241 if( _level_ ) \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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242 { \
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243 pol &= ~mask; \
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244 if( _up_ ) trig |= mask; \
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245 else trig &= ~mask; \
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246 } \
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247 else \
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248 { \
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249 pol |= mask; \
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250 if( !(_up_) ) trig |= mask; \
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251 else trig &= ~mask; \
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252 } \
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253 HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_POL, pol ); \
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254 HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG, trig ); \
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255 } \
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256 CYG_MACRO_END
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257
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258 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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259 CYG_MACRO_START \
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260 if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
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261 { \
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262 cyg_uint32 _ilevel_ = _level_; \
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263 while( _ilevel_ > 2 ) _ilevel_ -= 2; \
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264 cyg_hal_interrupt_level[_vector_] = _ilevel_; \
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265 } \
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266 CYG_MACRO_END
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267
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268 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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269
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270 //--------------------------------------------------------------------------
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271 // Control-C support.
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272
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273 #if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
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274
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275 # define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
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276
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277 externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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278
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279 #define HAL_CTRLC_ISR hal_ctrlc_isr
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280
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281 #endif
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282
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283 //--------------------------------------------------------------------------
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284 #endif // ifndef CYGONCE_HAL_PLF_INTR_H
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285 // End of plf_intr.h