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comparison packages/hal/mips/vrc4373/current/src/pmon.S @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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1 //========================================================================
2 //
3 // pmon.S
4 //
5 // Low-level entry points into PMON monitor.
6 //
7 //========================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //========================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): Red Hat, nickg
35 // Contributors: Red Hat, nickg
36 // Date: 1999-04-21
37 // Purpose:
38 // Description: Low-level entry points into PMON monitor.
39 // Usage:
40 //
41 //####DESCRIPTIONEND####
42 //
43 //========================================================================
44
45
46 #ifdef __mips16
47 /* This file contains 32 bit assembly code. */
48 .set nomips16
49 #endif
50
51 #if __mips < 3
52 /* This machine does not support 64-bit operations. */
53 #define ADDU addu
54 #define SUBU subu
55 #else
56 /* This machine supports 64-bit operations. */
57 #define ADDU daddu
58 #define SUBU dsubu
59 #endif
60
61
62 /* Standard MIPS register names: */
63 #define zero $0
64 #define z0 $0
65 #define v0 $2
66 #define v1 $3
67 #define a0 $4
68 #define a1 $5
69 #define a2 $6
70 #define a3 $7
71 #define t0 $8
72 #define t1 $9
73 #define t2 $10
74 #define t3 $11
75 #define t4 $12
76 #define t5 $13
77 #define t6 $14
78 #define t7 $15
79 #define s0 $16
80 #define s1 $17
81 #define s2 $18
82 #define s3 $19
83 #define s4 $20
84 #define s5 $21
85 #define s6 $22
86 #define s7 $23
87 #define t8 $24
88 #define t9 $25
89 #define k0 $26 /* kernel private register 0 */
90 #define k1 $27 /* kernel private register 1 */
91 #define gp $28 /* global data pointer */
92 #define sp $29 /* stack-pointer */
93 #define fp $30 /* frame-pointer */
94 #define ra $31 /* return address */
95 #define pc $pc /* pc, used on mips16 */
96
97 #define fp0 $f0
98 #define fp1 $f1
99
100 /* Useful memory constants: */
101 #define K0BASE 0x80000000
102 #ifndef __mips64
103 #define K1BASE 0xA0000000
104 #else
105 #define K1BASE 0xFFFFFFFFA0000000LL
106 #endif
107
108 #define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
109
110 /* Standard Co-Processor 0 register numbers: */
111 #define C0_COUNT $9 /* Count Register */
112 #define C0_SR $12 /* Status Register */
113 #define C0_CAUSE $13 /* last exception description */
114 #define C0_EPC $14 /* Exception error address */
115 #define C0_CONFIG $16 /* CPU configuration */
116
117 /* Standard Status Register bitmasks: */
118 #define SR_CU1 0x20000000 /* Mark CP1 as usable */
119 #define SR_FR 0x04000000 /* Enable MIPS III FP registers */
120 #define SR_BEV 0x00400000 /* Controls location of exception vectors */
121 #define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */
122
123 #define SR_KX 0x00000080 /* Kernel extended addressing enabled */
124 #define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
125 #define SR_UX 0x00000020 /* User extended addressing enabled */
126
127 /* Standard (R4000) cache operations. Taken from "MIPS R4000
128 Microprocessor User's Manual" 2nd edition: */
129
130 #define CACHE_I (0) /* primary instruction */
131 #define CACHE_D (1) /* primary data */
132 #define CACHE_SI (2) /* secondary instruction */
133 #define CACHE_SD (3) /* secondary data (or combined instruction/data) */
134
135 #define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
136 #define INDEX_LOAD_TAG (1)
137 #define INDEX_STORE_TAG (2)
138 #define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */
139 #define HIT_INVALIDATE (4)
140 #define CACHE_FILL (5) /* CACHE_I only */
141 #define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */
142 #define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */
143 #define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */
144
145 #define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
146
147 /* Individual cache operations: */
148 #define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
149 #define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
150 #define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
151 #define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
152
153 #define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
154 #define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
155 #define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
156 #define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
157
158 #define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
159 #define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
160 #define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
161 #define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
162
163 #define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
164 #define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
165
166 #define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
167 #define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
168 #define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
169 #define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
170
171 #define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
172 #define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
173 #define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
174
175 #define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
176 #define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
177 #define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
178
179 #define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
180 #define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
181
182 .text
183 .align 2
184
185 #ifdef LSI
186 #define PMON_VECTOR 0xffffffffbfc00200
187 #else
188 #define PMON_VECTOR 0xffffffffbfc00500
189 #endif
190
191 #ifndef __mips_eabi
192 /* Provide named functions for entry into the monitor: */
193 #define INDIRECT(name,index) \
194 .globl name; \
195 .ent name; \
196 .set noreorder; \
197 name: la $2,+(PMON_VECTOR+((index)*4)); \
198 lw $2,0($2); \
199 j $2; \
200 nop; \
201 .set reorder; \
202 .end name
203
204 #else
205 #define INDIRECT(name,index) \
206 .globl name; \
207 .ent name; \
208 .set noreorder; \
209 name: la $2,+(PMON_VECTOR+((index)*4)); \
210 lw $2,0($2); \
211 SUBU sp,sp,0x40; \
212 sd ra,0x38(sp); \
213 sd fp,0x30(sp); \
214 jal $2; \
215 move fp,sp; \
216 ld ra,0x38(sp); \
217 ld fp,0x30(sp); \
218 j ra; \
219 ADDU sp,sp,0x40; \
220 .set reorder; \
221 .end name
222 #endif
223
224
225 /* The following magic numbers are for the slots into the PMON monitor */
226 /* The first are used as the lo-level library run-time: */
227 INDIRECT(pmon_read,0)
228 INDIRECT(pmon_write,1)
229 INDIRECT(pmon_open,2)
230 INDIRECT(pmon_close,3)
231 /* The following are useful monitor routines: */
232 INDIRECT(pmon_ioctl,4)
233 INDIRECT(pmon_printf,5)
234 INDIRECT(pmon_vsprintf,6)
235 INDIRECT(pmon_ttctl,7)
236 INDIRECT(pmon_cliexit,8)
237 INDIRECT(pmon_getenv,9)
238 INDIRECT(pmon_onintr,10)
239 INDIRECT(pmon_flush_cache,11)
240 INDIRECT(pmon_exception,12)
241
242 /* The following routine is required by the "print()" function: */
243 .globl pmon_outbyte
244 .ent pmon_outbyte
245 .set noreorder
246 pmon_outbyte:
247 subu sp,sp,0x20 /* allocate stack space for string */
248 sd ra,0x18(sp) /* stack return address */
249 sd fp,0x10(sp) /* stack frame-pointer */
250 move fp,sp /* take a copy of the stack pointer */
251 /* We leave so much space on the stack for the string (16
252 characters), since the call to mon_printf seems to corrupt
253 the 8bytes at offset 8 into the string/stack. */
254 sb a0,0x00(sp) /* character to print */
255 sb z0,0x01(sp) /* NUL terminator */
256 jal pmon_printf /* and output the string */
257 move a0,sp /* take a copy of the string pointer {DELAY SLOT} */
258
259 move sp,fp /* recover stack pointer */
260 ld ra,0x18(sp) /* recover return address */
261 ld fp,0x10(sp) /* recover frame-pointer */
262 j ra /* return to the caller */
263 addu sp,sp,0x20 /* dump the stack space {DELAY SLOT} */
264 .set reorder
265 .end pmon_outbyte
266
267 /* EOF pmon.S */