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annotate packages/hal/mips/vrc4373/current/src/pmon.S @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 //========================================================================
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2 //
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3 // pmon.S
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4 //
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5 // Low-level entry points into PMON monitor.
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6 //
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7 //========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): Red Hat, nickg
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35 // Contributors: Red Hat, nickg
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36 // Date: 1999-04-21
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37 // Purpose:
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38 // Description: Low-level entry points into PMON monitor.
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39 // Usage:
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //========================================================================
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44
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45
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46 #ifdef __mips16
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47 /* This file contains 32 bit assembly code. */
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48 .set nomips16
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49 #endif
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50
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51 #if __mips < 3
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52 /* This machine does not support 64-bit operations. */
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53 #define ADDU addu
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54 #define SUBU subu
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55 #else
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56 /* This machine supports 64-bit operations. */
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57 #define ADDU daddu
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58 #define SUBU dsubu
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59 #endif
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60
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61
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62 /* Standard MIPS register names: */
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63 #define zero $0
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64 #define z0 $0
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65 #define v0 $2
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66 #define v1 $3
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67 #define a0 $4
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68 #define a1 $5
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69 #define a2 $6
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70 #define a3 $7
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71 #define t0 $8
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72 #define t1 $9
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73 #define t2 $10
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74 #define t3 $11
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75 #define t4 $12
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76 #define t5 $13
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77 #define t6 $14
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78 #define t7 $15
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79 #define s0 $16
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80 #define s1 $17
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81 #define s2 $18
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82 #define s3 $19
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83 #define s4 $20
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84 #define s5 $21
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85 #define s6 $22
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86 #define s7 $23
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87 #define t8 $24
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88 #define t9 $25
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89 #define k0 $26 /* kernel private register 0 */
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90 #define k1 $27 /* kernel private register 1 */
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91 #define gp $28 /* global data pointer */
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92 #define sp $29 /* stack-pointer */
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93 #define fp $30 /* frame-pointer */
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94 #define ra $31 /* return address */
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95 #define pc $pc /* pc, used on mips16 */
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96
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97 #define fp0 $f0
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98 #define fp1 $f1
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99
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100 /* Useful memory constants: */
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101 #define K0BASE 0x80000000
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102 #ifndef __mips64
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103 #define K1BASE 0xA0000000
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104 #else
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105 #define K1BASE 0xFFFFFFFFA0000000LL
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106 #endif
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107
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108 #define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
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109
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110 /* Standard Co-Processor 0 register numbers: */
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111 #define C0_COUNT $9 /* Count Register */
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112 #define C0_SR $12 /* Status Register */
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113 #define C0_CAUSE $13 /* last exception description */
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114 #define C0_EPC $14 /* Exception error address */
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115 #define C0_CONFIG $16 /* CPU configuration */
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116
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117 /* Standard Status Register bitmasks: */
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118 #define SR_CU1 0x20000000 /* Mark CP1 as usable */
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119 #define SR_FR 0x04000000 /* Enable MIPS III FP registers */
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120 #define SR_BEV 0x00400000 /* Controls location of exception vectors */
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121 #define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */
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122
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123 #define SR_KX 0x00000080 /* Kernel extended addressing enabled */
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124 #define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
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125 #define SR_UX 0x00000020 /* User extended addressing enabled */
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126
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127 /* Standard (R4000) cache operations. Taken from "MIPS R4000
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128 Microprocessor User's Manual" 2nd edition: */
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129
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130 #define CACHE_I (0) /* primary instruction */
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131 #define CACHE_D (1) /* primary data */
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132 #define CACHE_SI (2) /* secondary instruction */
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133 #define CACHE_SD (3) /* secondary data (or combined instruction/data) */
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134
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135 #define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
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136 #define INDEX_LOAD_TAG (1)
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137 #define INDEX_STORE_TAG (2)
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138 #define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */
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139 #define HIT_INVALIDATE (4)
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140 #define CACHE_FILL (5) /* CACHE_I only */
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141 #define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */
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142 #define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */
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143 #define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */
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144
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145 #define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
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146
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147 /* Individual cache operations: */
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148 #define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
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149 #define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
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150 #define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
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151 #define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
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152
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153 #define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
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154 #define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
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155 #define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
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156 #define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
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157
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158 #define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
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159 #define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
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160 #define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
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161 #define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
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162
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163 #define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
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164 #define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
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165
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166 #define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
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167 #define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
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168 #define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
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169 #define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
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170
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171 #define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
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172 #define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
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173 #define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
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174
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175 #define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
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176 #define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
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177 #define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
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178
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179 #define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
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180 #define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
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181
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182 .text
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183 .align 2
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184
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185 #ifdef LSI
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186 #define PMON_VECTOR 0xffffffffbfc00200
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187 #else
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188 #define PMON_VECTOR 0xffffffffbfc00500
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189 #endif
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190
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191 #ifndef __mips_eabi
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192 /* Provide named functions for entry into the monitor: */
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193 #define INDIRECT(name,index) \
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194 .globl name; \
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195 .ent name; \
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196 .set noreorder; \
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197 name: la $2,+(PMON_VECTOR+((index)*4)); \
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198 lw $2,0($2); \
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199 j $2; \
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200 nop; \
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201 .set reorder; \
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202 .end name
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203
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204 #else
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205 #define INDIRECT(name,index) \
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206 .globl name; \
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207 .ent name; \
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208 .set noreorder; \
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209 name: la $2,+(PMON_VECTOR+((index)*4)); \
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210 lw $2,0($2); \
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211 SUBU sp,sp,0x40; \
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212 sd ra,0x38(sp); \
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213 sd fp,0x30(sp); \
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214 jal $2; \
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215 move fp,sp; \
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216 ld ra,0x38(sp); \
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217 ld fp,0x30(sp); \
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218 j ra; \
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219 ADDU sp,sp,0x40; \
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220 .set reorder; \
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221 .end name
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222 #endif
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223
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224
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225 /* The following magic numbers are for the slots into the PMON monitor */
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226 /* The first are used as the lo-level library run-time: */
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227 INDIRECT(pmon_read,0)
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228 INDIRECT(pmon_write,1)
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229 INDIRECT(pmon_open,2)
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230 INDIRECT(pmon_close,3)
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231 /* The following are useful monitor routines: */
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232 INDIRECT(pmon_ioctl,4)
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233 INDIRECT(pmon_printf,5)
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234 INDIRECT(pmon_vsprintf,6)
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235 INDIRECT(pmon_ttctl,7)
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236 INDIRECT(pmon_cliexit,8)
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237 INDIRECT(pmon_getenv,9)
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238 INDIRECT(pmon_onintr,10)
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239 INDIRECT(pmon_flush_cache,11)
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240 INDIRECT(pmon_exception,12)
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241
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242 /* The following routine is required by the "print()" function: */
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243 .globl pmon_outbyte
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244 .ent pmon_outbyte
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245 .set noreorder
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246 pmon_outbyte:
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247 subu sp,sp,0x20 /* allocate stack space for string */
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248 sd ra,0x18(sp) /* stack return address */
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249 sd fp,0x10(sp) /* stack frame-pointer */
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250 move fp,sp /* take a copy of the stack pointer */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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251 /* We leave so much space on the stack for the string (16
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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252 characters), since the call to mon_printf seems to corrupt
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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253 the 8bytes at offset 8 into the string/stack. */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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254 sb a0,0x00(sp) /* character to print */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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255 sb z0,0x01(sp) /* NUL terminator */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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256 jal pmon_printf /* and output the string */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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257 move a0,sp /* take a copy of the string pointer {DELAY SLOT} */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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258
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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259 move sp,fp /* recover stack pointer */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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260 ld ra,0x18(sp) /* recover return address */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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261 ld fp,0x10(sp) /* recover frame-pointer */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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262 j ra /* return to the caller */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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263 addu sp,sp,0x20 /* dump the stack space {DELAY SLOT} */
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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264 .set reorder
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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265 .end pmon_outbyte
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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266
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
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267 /* EOF pmon.S */