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comparison packages/hal/sh/arch/current/include/hal_io.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 0d0f03f76f6a
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75:41bf073c0c32 76:435cced73e2f
1 #ifndef CYGONCE_HAL_IO_H
2 #define CYGONCE_HAL_IO_H
3
4 //=============================================================================
5 //
6 // hal_io.h
7 //
8 // HAL device IO register support.
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 //=============================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): nickg
38 // Contributors:nickg, jskov
39 // Date: 1999-04-24
40 // Purpose: Define IO register support
41 // Description: The macros defined here provide the HAL APIs for handling
42 // device IO control registers.
43 //
44 // Usage:
45 // #include <cyg/hal/hal_io.h>
46 // ...
47 //
48 //
49 //####DESCRIPTIONEND####
50 //
51 //=============================================================================
52
53 #include <cyg/infra/cyg_type.h>
54
55 //-----------------------------------------------------------------------------
56 // IO Register address.
57 // This type is for recording the address of an IO register.
58
59 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
60
61 //-----------------------------------------------------------------------------
62 // BYTE Register access.
63 // Individual and vectorized access to 8 bit registers.
64
65 #define HAL_READ_UINT8( _register_, _value_ ) \
66 CYG_MACRO_START \
67 ((_value_) = *((volatile CYG_BYTE *)(_register_))); \
68 CYG_MACRO_END
69
70 #define HAL_WRITE_UINT8( _register_, _value_ ) \
71 CYG_MACRO_START \
72 (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
73 CYG_MACRO_END
74
75 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
76 CYG_MACRO_START \
77 cyg_count32 _i_,_j_; \
78 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
79 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
80 } \
81 CYG_MACRO_END
82
83 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
84 CYG_MACRO_START \
85 cyg_count32 _i_,_j_; \
86 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
87 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
88 } \
89 CYG_MACRO_END
90
91
92 //-----------------------------------------------------------------------------
93 // 16 bit access.
94 // Individual and vectorized access to 16 bit registers.
95
96 #define HAL_READ_UINT16( _register_, _value_ ) \
97 CYG_MACRO_START \
98 ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \
99 CYG_MACRO_END
100
101 #define HAL_WRITE_UINT16( _register_, _value_ ) \
102 CYG_MACRO_START \
103 (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \
104 CYG_MACRO_END
105
106 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
107 CYG_MACRO_START \
108 cyg_count32 _i_,_j_; \
109 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
110 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
111 } \
112 CYG_MACRO_END
113
114 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
115 CYG_MACRO_START \
116 cyg_count32 _i_,_j_; \
117 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
118 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
119 } \
120 CYG_MACRO_END
121
122 //-----------------------------------------------------------------------------
123 // 32 bit access.
124 // Individual and vectorized access to 32 bit registers.
125
126 #define HAL_READ_UINT32( _register_, _value_ ) \
127 CYG_MACRO_START \
128 ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \
129 CYG_MACRO_END
130
131 #define HAL_WRITE_UINT32( _register_, _value_ ) \
132 CYG_MACRO_START \
133 (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \
134 CYG_MACRO_END
135
136 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
137 CYG_MACRO_START \
138 cyg_count32 _i_,_j_; \
139 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
140 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
141 } \
142 CYG_MACRO_END
143
144 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
145 CYG_MACRO_START \
146 cyg_count32 _i_,_j_; \
147 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
148 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
149 } \
150 CYG_MACRO_END
151
152 //-----------------------------------------------------------------------------
153 #endif // ifndef CYGONCE_HAL_IO_H
154 // End of hal_io.h