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annotate packages/hal/sh/arch/current/include/hal_io.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 0d0f03f76f6a
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 #ifndef CYGONCE_HAL_IO_H
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2 #define CYGONCE_HAL_IO_H
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3
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4 //=============================================================================
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5 //
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6 // hal_io.h
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7 //
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8 // HAL device IO register support.
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg
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38 // Contributors:nickg, jskov
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39 // Date: 1999-04-24
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40 // Purpose: Define IO register support
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // device IO control registers.
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43 //
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44 // Usage:
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45 // #include <cyg/hal/hal_io.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //=============================================================================
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52
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53 #include <cyg/infra/cyg_type.h>
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54
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55 //-----------------------------------------------------------------------------
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56 // IO Register address.
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57 // This type is for recording the address of an IO register.
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58
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59 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
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60
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61 //-----------------------------------------------------------------------------
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62 // BYTE Register access.
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63 // Individual and vectorized access to 8 bit registers.
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64
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65 #define HAL_READ_UINT8( _register_, _value_ ) \
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66 CYG_MACRO_START \
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67 ((_value_) = *((volatile CYG_BYTE *)(_register_))); \
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68 CYG_MACRO_END
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69
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70 #define HAL_WRITE_UINT8( _register_, _value_ ) \
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71 CYG_MACRO_START \
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72 (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
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73 CYG_MACRO_END
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74
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75 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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76 CYG_MACRO_START \
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77 cyg_count32 _i_,_j_; \
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78 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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79 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
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80 } \
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81 CYG_MACRO_END
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82
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83 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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84 CYG_MACRO_START \
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85 cyg_count32 _i_,_j_; \
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86 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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87 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
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88 } \
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89 CYG_MACRO_END
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90
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91
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92 //-----------------------------------------------------------------------------
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93 // 16 bit access.
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94 // Individual and vectorized access to 16 bit registers.
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95
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96 #define HAL_READ_UINT16( _register_, _value_ ) \
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97 CYG_MACRO_START \
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98 ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \
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99 CYG_MACRO_END
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100
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101 #define HAL_WRITE_UINT16( _register_, _value_ ) \
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102 CYG_MACRO_START \
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103 (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \
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104 CYG_MACRO_END
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105
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106 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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107 CYG_MACRO_START \
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108 cyg_count32 _i_,_j_; \
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109 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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110 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
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111 } \
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112 CYG_MACRO_END
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113
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114 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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115 CYG_MACRO_START \
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116 cyg_count32 _i_,_j_; \
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117 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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118 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
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119 } \
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120 CYG_MACRO_END
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121
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122 //-----------------------------------------------------------------------------
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123 // 32 bit access.
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124 // Individual and vectorized access to 32 bit registers.
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125
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126 #define HAL_READ_UINT32( _register_, _value_ ) \
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127 CYG_MACRO_START \
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128 ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \
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129 CYG_MACRO_END
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130
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131 #define HAL_WRITE_UINT32( _register_, _value_ ) \
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132 CYG_MACRO_START \
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133 (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \
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134 CYG_MACRO_END
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135
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136 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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137 CYG_MACRO_START \
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138 cyg_count32 _i_,_j_; \
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139 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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140 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
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141 } \
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142 CYG_MACRO_END
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143
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144 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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145 CYG_MACRO_START \
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146 cyg_count32 _i_,_j_; \
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147 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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148 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
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149 } \
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150 CYG_MACRO_END
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151
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152 //-----------------------------------------------------------------------------
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153 #endif // ifndef CYGONCE_HAL_IO_H
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154 // End of hal_io.h