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comparison packages/hal/sh/arch/current/include/hal_cache.h @ 84:489eb5632bc3 ecos-sw-2000-04-28

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Merge from eCos master repository on 2000-04-28-18:44:39-BST
author jlarmour
date Fri, 28 Apr 2000 18:18:36 +0000
parents 59d97b6ba612
children 0c2b7be0d798
comparison
equal deleted inserted replaced
83:1094d5fdd3e0 84:489eb5632bc3
59 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions 59 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
60 60
61 //----------------------------------------------------------------------------- 61 //-----------------------------------------------------------------------------
62 // Cache dimensions - one unified cache 62 // Cache dimensions - one unified cache
63 63
64 #define HAL_CACHE_UNIFIED
65
64 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE 66 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
65 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE 67 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
66 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS 68 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
67 69
68 // Cache addressing information 70 // Cache addressing information
77 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) 79 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
78 80
79 //----------------------------------------------------------------------------- 81 //-----------------------------------------------------------------------------
80 // Global control of cache 82 // Global control of cache
81 83
84 // This is all handled in assembly (see vectors.S) due to a requirement about
85 // not fiddling the cache from cachable memory.
86
87 externC void cyg_hal_cache_enable(void);
88 externC void cyg_hal_cache_disable(void);
89 externC void cyg_hal_cache_invalidate_all(void);
90 externC void cyg_hal_cache_sync(void);
91 externC void cyg_hal_cache_write_mode(int mode);
82 92
83 // Enable the cache 93 // Enable the cache
84 #define HAL_UCACHE_ENABLE() \ 94 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
85 CYG_MACRO_START \
86 register cyg_uint32 __tmp; \
87 HAL_READ_UINT32(CYGARC_REG_CCR, __tmp); \
88 __tmp |= CYGARC_REG_CCR_CE; \
89 HAL_WRITE_UINT32(CYGARC_REG_CCR, __tmp); \
90 CYG_MACRO_END
91 95
92 // Disable the cache 96 // Disable the cache
93 #define HAL_UCACHE_DISABLE() \ 97 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
94 CYG_MACRO_START \
95 register cyg_uint32 __tmp; \
96 HAL_READ_UINT32(CYGARC_REG_CCR, __tmp); \
97 __tmp &= ~CYGARC_REG_CCR_CE; \
98 HAL_WRITE_UINT32(CYGARC_REG_CCR, __tmp); \
99 CYG_MACRO_END
100 98
101 // Invalidate the entire cache 99 // Invalidate the entire cache
102 // Note: The CF bit does not cause any data to be written back before 100 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
103 // invalidation of the cache.
104 #define HAL_UCACHE_INVALIDATE_ALL() \
105 CYG_MACRO_START \
106 register cyg_uint32 __tmp; \
107 HAL_READ_UINT32(CYGARC_REG_CCR, __tmp); \
108 __tmp |= CYGARC_REG_CCR_CF; \
109 HAL_WRITE_UINT32(CYGARC_REG_CCR, __tmp); \
110 CYG_MACRO_END
111 101
112 // Synchronize the contents of the cache with memory. 102 // Synchronize the contents of the cache with memory.
113 #define HAL_UCACHE_SYNC() \ 103 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
114 CYG_MACRO_START \ 104
115 register cyg_uint32* __p; \ 105 // Query the state of the cache (does not affect the caching)
116 register cyg_uint32* __top = (cyg_uint32*)CYGARC_REG_CACHE_ADDRESS_TOP; \
117 for (__p = (cyg_uint32*)CYGARC_REG_CACHE_ADDRESS_BASE; \
118 __p < __top; \
119 __p += CYGARC_REG_CACHE_ADDRESS_STEP/sizeof(cyg_uint32)) \
120 *__p = CYGARC_REG_CACHE_ADDRESS_FLUSH; \
121 CYG_MACRO_END
122
123 // Query the state of the cache
124 #define HAL_UCACHE_IS_ENABLED(_state_) \ 106 #define HAL_UCACHE_IS_ENABLED(_state_) \
125 CYG_MACRO_START \ 107 CYG_MACRO_START \
126 HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \ 108 HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \
127 (_state_) &= ~CYGARC_REG_CCR_CE; \ 109 (_state_) &= ~CYGARC_REG_CCR_CE; \
128 CYG_MACRO_END 110 CYG_MACRO_END
129 111
130 // Set the cache refill burst size 112 // Set the cache refill burst size
131 //#define HAL_UCACHE_BURST_SIZE(_size_) 113 //#define HAL_UCACHE_BURST_SIZE(_size_)
132 114
133 // Set the cache write mode 115 // Set the cache write mode
134 #define HAL_UCACHE_WRITE_MODE( _mode_ ) \ 116 #define HAL_UCACHE_WRITE_MODE( _mode_ ) cyg_hal_cache_write_mode(_mode_)
135 CYG_MACRO_START \
136 register cyg_uint32 __tmp; \
137 HAL_READ_UINT32(CYGARC_REG_CCR, __tmp); \
138 __tmp &= ~CYGARC_REG_CCR_CB; \
139 if (HAL_UCACHE_WRITEBACK_MODE == (_mode_)) \
140 __tmp |= CYGARC_REG_CCR_CB; \
141 HAL_WRITE_UINT32(CYGARC_REG_CCR, __tmp); \
142 CYG_MACRO_END
143 117
144 #define HAL_UCACHE_WRITETHRU_MODE 0 118 #define HAL_UCACHE_WRITETHRU_MODE 0
145 #define HAL_UCACHE_WRITEBACK_MODE 1 119 #define HAL_UCACHE_WRITEBACK_MODE 1
146 120
147 // Load the contents of the given address range into the cache 121 // Load the contents of the given address range into the cache