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annotate packages/hal/sh/arch/current/include/hal_cache.h @ 84:489eb5632bc3 ecos-sw-2000-04-28

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Merge from eCos master repository on 2000-04-28-18:44:39-BST
author jlarmour
date Fri, 28 Apr 2000 18:18:36 +0000
parents 59d97b6ba612
children 0c2b7be0d798
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): jskov
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38 // Contributors:jskov
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39 // Date: 1999-04-23
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40 // Purpose: Cache control API
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // cache control operations.
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43 // Usage:
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44 // #include <cyg/hal/hal_cache.h>
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45 // ...
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46 //
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //=============================================================================
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51
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52 #include <pkgconf/system.h>
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53 #include <pkgconf/hal.h>
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54 #include <cyg/infra/cyg_type.h>
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55 #include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros
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56
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57 #include CYGBLD_HAL_CPU_MODULES_H // cache module specs
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59 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
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60
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61 //-----------------------------------------------------------------------------
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62 // Cache dimensions - one unified cache
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63
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64 #define HAL_CACHE_UNIFIED
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66 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
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67 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
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68 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
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70 // Cache addressing information
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71 #define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE
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72 #define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP
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73 #define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP
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74
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75 // Writing this to a cache address entry forces a flush of the line if
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76 // it is dirty.
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77 #define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH
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79 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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80
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81 //-----------------------------------------------------------------------------
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82 // Global control of cache
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83
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84 // This is all handled in assembly (see vectors.S) due to a requirement about
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85 // not fiddling the cache from cachable memory.
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86
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87 externC void cyg_hal_cache_enable(void);
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88 externC void cyg_hal_cache_disable(void);
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89 externC void cyg_hal_cache_invalidate_all(void);
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90 externC void cyg_hal_cache_sync(void);
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91 externC void cyg_hal_cache_write_mode(int mode);
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92
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93 // Enable the cache
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94 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
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95
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96 // Disable the cache
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97 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
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98
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99 // Invalidate the entire cache
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100 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
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101
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102 // Synchronize the contents of the cache with memory.
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103 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
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104
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105 // Query the state of the cache (does not affect the caching)
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106 #define HAL_UCACHE_IS_ENABLED(_state_) \
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107 CYG_MACRO_START \
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108 HAL_READ_UINT32(CYGARC_REG_CCR, (_state_)); \
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109 (_state_) &= ~CYGARC_REG_CCR_CE; \
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110 CYG_MACRO_END
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111
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112 // Set the cache refill burst size
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113 //#define HAL_UCACHE_BURST_SIZE(_size_)
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114
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115 // Set the cache write mode
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116 #define HAL_UCACHE_WRITE_MODE( _mode_ ) cyg_hal_cache_write_mode(_mode_)
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117
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118 #define HAL_UCACHE_WRITETHRU_MODE 0
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119 #define HAL_UCACHE_WRITEBACK_MODE 1
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120
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121 // Load the contents of the given address range into the cache
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122 // and then lock the cache so that it stays there.
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123 //#define HAL_UCACHE_LOCK(_base_, _size_)
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124
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125 // Undo a previous lock operation
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126 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
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127
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128 // Unlock entire cache
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129 //#define HAL_UCACHE_UNLOCK_ALL()
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130
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131 //-----------------------------------------------------------------------------
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132 // Cache line control
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133
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134 // Allocate cache lines for the given address range without reading its
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135 // contents from memory.
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136 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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137
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138 // Write dirty cache lines to memory and invalidate the cache entries
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139 // for the given address range.
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140 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
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141
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142 // Invalidate cache lines in the given range without writing to memory.
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143 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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144
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145 // Write dirty cache lines to memory for the given address range.
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146 //#define HAL_UCACHE_STORE( _base_ , _size_ )
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147
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148 // Preread the given range into the cache with the intention of reading
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149 // from it later.
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150 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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151
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152 // Preread the given range into the cache with the intention of writing
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153 // to it later.
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154 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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155
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156 // Allocate and zero the cache lines associated with the given range.
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157 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
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158
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159
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160 //-----------------------------------------------------------------------------
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161 // Data and instruction cache macros map onto the both-cache macros
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162
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163 //-----------------------------------------------------------------------------
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164 // Global control of data cache
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165
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166 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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167 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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168 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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169 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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170
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171 // Enable the data cache
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172 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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173
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174 // Disable the data cache
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175 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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176
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177 // Invalidate the entire cache
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178 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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179
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180 // Synchronize the contents of the cache with memory.
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181 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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182
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183 // Query the state of the data cache
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184 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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185
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186 // Set the data cache refill burst size
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187 //#define HAL_DCACHE_BURST_SIZE(_size_)
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188
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189 // Set the data cache write mode
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190 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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191
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192 //#define HAL_DCACHE_WRITETHRU_MODE 0
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193 //#define HAL_DCACHE_WRITEBACK_MODE 1
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194
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195 // Load the contents of the given address range into the data cache
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196 // and then lock the cache so that it stays there.
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197 //#define HAL_DCACHE_LOCK(_base_, _size_)
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198
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199 // Undo a previous lock operation
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200 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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201
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202 // Unlock entire cache
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203 //#define HAL_DCACHE_UNLOCK_ALL()
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204
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205 //-----------------------------------------------------------------------------
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206 // Data cache line control
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207
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208 // Allocate cache lines for the given address range without reading its
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209 // contents from memory.
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210 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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211
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212 // Write dirty cache lines to memory and invalidate the cache entries
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213 // for the given address range.
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214 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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215
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216 // Invalidate cache lines in the given range without writing to memory.
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217 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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218
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219 // Write dirty cache lines to memory for the given address range.
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220 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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221
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222 // Preread the given range into the cache with the intention of reading
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223 // from it later.
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224 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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225
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226 // Preread the given range into the cache with the intention of writing
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227 // to it later.
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228 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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229
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230 // Allocate and zero the cache lines associated with the given range.
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231 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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232
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233 //-----------------------------------------------------------------------------
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234 // Global control of Instruction cache
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235
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236 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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237 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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238 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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239 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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240
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241 // Enable the instruction cache
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242 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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243
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244 // Disable the instruction cache
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245 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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246
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247 // Invalidate the entire cache
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248 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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249
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250
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251 // Synchronize the contents of the cache with memory.
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252 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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253
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254 // Query the state of the instruction cache
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255 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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256
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257 // Set the instruction cache refill burst size
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258 //#define HAL_ICACHE_BURST_SIZE(_size_)
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259
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260 // Load the contents of the given address range into the instruction cache
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261 // and then lock the cache so that it stays there.
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262
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263 //#define HAL_ICACHE_LOCK(_base_, _size_)
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264
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265 // Undo a previous lock operation
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266 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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267
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268 // Unlock entire cache
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269 //#define HAL_ICACHE_UNLOCK_ALL()
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270
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271 //-----------------------------------------------------------------------------
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272 // Instruction cache line control
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273
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274 // Invalidate cache lines in the given range without writing to memory.
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275 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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276
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277 //-----------------------------------------------------------------------------
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278 #endif // ifndef CYGONCE_HAL_CACHE_H
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279 // End of hal_cache.h