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comparison packages/hal/arm/aeb/current/include/hal_platform_setup.h @ 46:797268ecc331 ecos-sw-1999-10-19

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Merge from eCos master repository on 1999-10-19-18:55:31-BST
author jlarmour
date Tue, 19 Oct 1999 19:19:52 +0000
parents 41bd4f3a90de
children c38311975d4f
comparison
equal deleted inserted replaced
45:91d213c0da48 46:797268ecc331
53 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048 53 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
54 #endif 54 #endif
55 55
56 #ifdef CYGHWR_HAL_ARM_AEB_REVISION_C 56 #ifdef CYGHWR_HAL_ARM_AEB_REVISION_C
57 // AEB rev C has 256kB of memory. Cache is working (set cachable) 57 // AEB rev C has 256kB of memory. Cache is working (set cachable)
58 #if 0
58 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04 59 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04
59 #define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000 60 #define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
61 #else
62 // FIXME: There is a cache problem of some sort. Either eCos or the
63 // chip. Leave cache disabled till I find the time to fix it. Jesper
64 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007804
65 #define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
66 #endif
60 #else 67 #else
61 // AEB rev B has 128kB of memory. Cache is broken (clear cachable) 68 // AEB rev B has 128kB of memory. Cache is broken (clear cachable)
62 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00028000,0x00007804 69 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00028000,0x00007804
63 #define AEB_BAD .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000 70 #define AEB_BAD .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000
64 #endif 71 #endif