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comparison packages/hal/powerpc/ppc40x/current/include/variant.inc @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children 289bf90c6a9b
comparison
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135:3bc2abeae9ff 136:a9ac27ec7abc
55 55
56 #include <cyg/hal/arch.inc> 56 #include <cyg/hal/arch.inc>
57 57
58 ##----------------------------------------------------------------------------- 58 ##-----------------------------------------------------------------------------
59 ## PPC40x defined vectors 59 ## PPC40x defined vectors
60
61 ## Special code to handle the various timers which generate non-standard
62 ## interrupts. There are really three VSRs here, each 0x10 apart.
63 .macro timer_vector name
64 .p2align 8
65 .globl __exception_\name
66 __exception_\name:
67 # Variable timer interrupt
68 mtspr SPRG1,r3 # stash some work registers away
69 mtspr SPRG2,r4
70 li r4,0x1000 # vector offset
71 b 0f
72 # Fixed timer interrupt
73 mtspr SPRG1,r3 # stash some work registers away
74 mtspr SPRG2,r4
75 li r4,0x1010 # vector offset
76 b 0f
77 # Watchdog timer interrupt
78 mtspr SPRG1,r3 # stash some work registers away
79 mtspr SPRG2,r4
80 li r4,0x1020 # vector offset
81 0: mtspr SPRG3,r5
82 lwi r3,hal_vsr_table+(0x1000>>6) # table base
83 lwz r3,0(r3) # address of vsr
84 mflr r5 # save link register
85 mtlr r3 # put vsr address into it
86 mr r3,r4 # original vector
87 mfcr r4 # stash CR
88 blr # go to common code
89 .endm
60 90
61 .macro hal_extra_vectors 91 .macro hal_extra_vectors
92 timer_vector ppc40x_timers
93 exception_vector data_TLB_miss
94 exception_vector instr_TLB_miss
95 exception_vector reserved_01300
96 exception_vector reserved_01400
97 exception_vector reserved_01500
98 exception_vector reserved_01600
99 exception_vector reserved_01700
100 exception_vector reserved_01800
101 exception_vector reserved_01900
102 exception_vector reserved_01A00
103 exception_vector reserved_01B00
104 exception_vector reserved_01C00
105 exception_vector reserved_01D00
106 exception_vector reserved_01E00
107 exception_vector reserved_01F00
108 exception_vector ppc40x_debug
62 .endm 109 .endm
63 110
64 ##----------------------------------------------------------------------------- 111 ##-----------------------------------------------------------------------------
65 ## PPC40x CPU initialization 112 ## PPC40x CPU initialization
66 ## 113 ##
106 blt 1b # loop if not yet done 153 blt 1b # loop if not yet done
107 2: 154 2:
108 155
109 # Ensure that the vectors will come from 0x0000 156 # Ensure that the vectors will come from 0x0000
110 lwi r4,0 157 lwi r4,0
111 mtspr EVPR,r4 158 mtspr SPR_EVPR,r4
112 #endif 159 #endif
113 160
114 # Next initialize the VSR table. This happens whether the 161 # Next initialize the VSR table. This happens whether the
115 # vectors were copied to RAM or not. 162 # vectors were copied to RAM or not.
116 163
127 # Then fill in the special vectors 174 # Then fill in the special vectors
128 lwi r3,cyg_hal_default_interrupt_vsr 175 lwi r3,cyg_hal_default_interrupt_vsr
129 lwi r4,hal_vsr_table 176 lwi r4,hal_vsr_table
130 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) 177 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
131 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) 178 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
179 stw r3,CYGNUM_HAL_VECTOR_TIMERS*4(r4)
132 .endm 180 .endm
133 181
134 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) 182 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
135 183
136 # Initialize the VSR table entries 184 # Initialize the VSR table entries
140 .macro hal_mon_init 188 .macro hal_mon_init
141 lwi r3,cyg_hal_default_interrupt_vsr 189 lwi r3,cyg_hal_default_interrupt_vsr
142 lwi r4,hal_vsr_table 190 lwi r4,hal_vsr_table
143 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) 191 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
144 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) 192 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
193 stw r3,CYGNUM_HAL_VECTOR_TIMERS*4(r4)
145 .endm 194 .endm
146 195
147 196
148 #else 197 #else
149 198
168 217
169 ##----------------------------------------------------------------------------- 218 ##-----------------------------------------------------------------------------
170 ## Indicate that the ISR tables are defined in variant.S 219 ## Indicate that the ISR tables are defined in variant.S
171 220
172 #define CYG_HAL_PPC_ISR_TABLES_DEFINED 221 #define CYG_HAL_PPC_ISR_TABLES_DEFINED
222
223 ##-----------------------------------------------------------------------------
224 ## MPC4xx interrupt handling.
225
226 ## Decode the EXISR appropriately
227
228 #define CYGPKG_HAL_POWERPC_INTC_DEFINED
229 # decode the interrupt
230 # the interrupt vector will be 0x500 or 0x10x0
231 # 0x0500 = external, must be decoded via EXISR
232 # 0x10X0 = timer, X is the timer type
233 # r3 used as scratch
234 .macro hal_intc_decode dreg,state
235 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
236 extrwi. \dreg,\dreg,1,19 # isolate bit 19
237 beq 0f # timer interrupt = 1
238 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
239 extrwi \dreg,\dreg,2,26 # isolate bits 26-27
240 addi \dreg,\dreg,CYGNUM_HAL_INTERRUPT_VAR_TIMER # FIXME
241 b 1f
242 0: mfdcr r3,DCR_EXISR # Interrupt status register
243 lwi \dreg,0x8FF0001F # significant bits
244 and \dreg,\dreg,r3
245 cntlzw r3,\dreg # find highest "1" bit
246 slwi r3,r3,2
247 lwi \dreg,EXISR_TAB # convert bit # to signal #
248 lwz \dreg,0(\dreg)
249 1: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
250 slwi \dreg,\dreg,2 # convert to byte offset.
251 .endm
252
173 253
174 #------------------------------------------------------------------------------ 254 #------------------------------------------------------------------------------
175 #endif // ifndef CYGONCE_HAL_VARIANT_INC 255 #endif // ifndef CYGONCE_HAL_VARIANT_INC
176 # end of variant.inc 256 # end of variant.inc