Mercurial > flash_v2

annotate packages/hal/powerpc/ppc40x/current/include/variant.inc @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children 289bf90c6a9b
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## PPC40x family assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.1 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://www.redhat.com/
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): jskov
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37 ## Contributors:jskov, gthomas
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38 ## Date: 2000-08-27
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39 ## Purpose: MPCxxx family definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the PPC40x CPU family.
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42 ## Usage:
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43 ## #include <cyg/hal/variant.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <pkgconf/hal.h>
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52
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53 #undef CYG_MSR_COMMON
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54 #define CYG_MSR_COMMON (MSR_ME | MSR_RI)
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55
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56 #include <cyg/hal/arch.inc>
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57
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58 ##-----------------------------------------------------------------------------
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59 ## PPC40x defined vectors
136
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60
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61 ## Special code to handle the various timers which generate non-standard
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62 ## interrupts. There are really three VSRs here, each 0x10 apart.
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63 .macro timer_vector name
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64 .p2align 8
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65 .globl __exception_\name
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66 __exception_\name:
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67 # Variable timer interrupt
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68 mtspr SPRG1,r3 # stash some work registers away
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69 mtspr SPRG2,r4
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70 li r4,0x1000 # vector offset
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71 b 0f
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72 # Fixed timer interrupt
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73 mtspr SPRG1,r3 # stash some work registers away
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74 mtspr SPRG2,r4
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75 li r4,0x1010 # vector offset
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76 b 0f
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77 # Watchdog timer interrupt
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78 mtspr SPRG1,r3 # stash some work registers away
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79 mtspr SPRG2,r4
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80 li r4,0x1020 # vector offset
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81 0: mtspr SPRG3,r5
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82 lwi r3,hal_vsr_table+(0x1000>>6) # table base
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83 lwz r3,0(r3) # address of vsr
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84 mflr r5 # save link register
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85 mtlr r3 # put vsr address into it
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86 mr r3,r4 # original vector
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87 mfcr r4 # stash CR
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88 blr # go to common code
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89 .endm
134
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90
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91 .macro hal_extra_vectors
136
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92 timer_vector ppc40x_timers
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93 exception_vector data_TLB_miss
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94 exception_vector instr_TLB_miss
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95 exception_vector reserved_01300
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96 exception_vector reserved_01400
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97 exception_vector reserved_01500
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98 exception_vector reserved_01600
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99 exception_vector reserved_01700
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100 exception_vector reserved_01800
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101 exception_vector reserved_01900
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102 exception_vector reserved_01A00
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103 exception_vector reserved_01B00
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104 exception_vector reserved_01C00
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105 exception_vector reserved_01D00
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106 exception_vector reserved_01E00
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107 exception_vector reserved_01F00
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108 exception_vector ppc40x_debug
134
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109 .endm
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110
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111 ##-----------------------------------------------------------------------------
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112 ## PPC40x CPU initialization
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113 ##
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114 ## Initialize CPU to a post-reset state, ensuring the ground doesn''t
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115 ## shift under us while we try to set things up.
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116
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117 .macro hal_cpu_init
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118 # Set up MSR (disable MMU for now)
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119 lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
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120 sync
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121 mfmsr r4
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122 mtmsr r3
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123 sync
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124 .endm
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125
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126 ##-----------------------------------------------------------------------------
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127 ## PPC40x monitor initialization
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128
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129 #ifndef CYGPKG_HAL_PPC_MON_DEFINED
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130
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131 #if defined(CYG_HAL_STARTUP_ROM) || \
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132 ( defined(CYG_HAL_STARTUP_RAM) && \
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133 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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134
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135 .macro hal_mon_init
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136 #ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
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137 # If we are starting up from ROM and want vectors in RAM
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138 # or we are starting in RAM and NOT using a ROM monitor,
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139 # copy exception handler code to 0.
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140 lwi r3,rom_vectors # r3 = rom start
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141 lwi r4,0 # r4 = ram start
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142 lwi r5,rom_vectors_end # r5 = rom end
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143 cmplw r3,r5 # skip if no vectors
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144 beq 2f
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145
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146 subi r3,r3,4
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147 subi r4,r4,4
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148 subi r5,r5,4
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149 1:
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150 lwzu r0,4(r3) # get word from ROM
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151 stwu r0,4(r4) # store in RAM
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152 cmplw r3,r5 # compare
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153 blt 1b # loop if not yet done
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154 2:
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155
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156 # Ensure that the vectors will come from 0x0000
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157 lwi r4,0
136
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158 mtspr SPR_EVPR,r4
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159 #endif
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160
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161 # Next initialize the VSR table. This happens whether the
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162 # vectors were copied to RAM or not.
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163
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164 # First fill with exception handlers
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165 lwi r3,cyg_hal_default_exception_vsr
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166 lwi r4,hal_vsr_table
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167 subi r4,r4,4
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168 li r5,CYGNUM_HAL_VSR_COUNT
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169 1: stwu r3,4(r4)
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170 subi r5,r5,1
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171 cmpwi r5,0
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172 bne 1b
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173
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174 # Then fill in the special vectors
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175 lwi r3,cyg_hal_default_interrupt_vsr
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176 lwi r4,hal_vsr_table
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177 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
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178 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
136
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179 stw r3,CYGNUM_HAL_VECTOR_TIMERS*4(r4)
134
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180 .endm
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181
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182 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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183
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184 # Initialize the VSR table entries
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185 # We only take control of the interrupt vectors,
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186 # the rest are left to the ROM for now...
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187
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188 .macro hal_mon_init
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189 lwi r3,cyg_hal_default_interrupt_vsr
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190 lwi r4,hal_vsr_table
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191 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
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192 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
136
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193 stw r3,CYGNUM_HAL_VECTOR_TIMERS*4(r4)
134
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194 .endm
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195
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196
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197 #else
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198
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199 .macro hal_mon_init
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200
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201 .endm
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202
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203 #endif
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204
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205
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206 #define CYGPKG_HAL_PPC_MON_DEFINED
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207
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208 #endif // CYGPKG_HAL_PPC_MON_DEFINED
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209
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210 ##-----------------------------------------------------------------------------
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211 ## PPC40x exception state handling
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212 .macro hal_variant_save regs
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213 .endm
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214
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215 .macro hal_variant_load regs
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216 .endm
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217
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218 ##-----------------------------------------------------------------------------
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219 ## Indicate that the ISR tables are defined in variant.S
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220
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221 #define CYG_HAL_PPC_ISR_TABLES_DEFINED
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222
136
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223 ##-----------------------------------------------------------------------------
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224 ## MPC4xx interrupt handling.
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225
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226 ## Decode the EXISR appropriately
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227
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228 #define CYGPKG_HAL_POWERPC_INTC_DEFINED
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229 # decode the interrupt
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230 # the interrupt vector will be 0x500 or 0x10x0
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231 # 0x0500 = external, must be decoded via EXISR
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232 # 0x10X0 = timer, X is the timer type
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233 # r3 used as scratch
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234 .macro hal_intc_decode dreg,state
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235 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
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236 extrwi. \dreg,\dreg,1,19 # isolate bit 19
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237 beq 0f # timer interrupt = 1
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238 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
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239 extrwi \dreg,\dreg,2,26 # isolate bits 26-27
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240 addi \dreg,\dreg,CYGNUM_HAL_INTERRUPT_VAR_TIMER # FIXME
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241 b 1f
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242 0: mfdcr r3,DCR_EXISR # Interrupt status register
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243 lwi \dreg,0x8FF0001F # significant bits
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244 and \dreg,\dreg,r3
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245 cntlzw r3,\dreg # find highest "1" bit
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246 slwi r3,r3,2
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247 lwi \dreg,EXISR_TAB # convert bit # to signal #
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248 lwz \dreg,0(\dreg)
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249 1: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
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250 slwi \dreg,\dreg,2 # convert to byte offset.
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251 .endm
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252
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253
134
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254 #------------------------------------------------------------------------------
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255 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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256 # end of variant.inc