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comparison packages/hal/powerpc/arch/current/include/hal_cache.h @ 70:c5536bad4c24 ecos-sw-2000-02-11

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Merge from eCos master repository on 2000-02-11-15:46:40-GMT
author jlarmour
date Fri, 11 Feb 2000 16:47:32 +0000
parents f74b2666b30d
children da3908c9cd10
comparison
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69:9a9babddf7e7 70:c5536bad4c24
33 //####COPYRIGHTEND#### 33 //####COPYRIGHTEND####
34 //============================================================================= 34 //=============================================================================
35 //#####DESCRIPTIONBEGIN#### 35 //#####DESCRIPTIONBEGIN####
36 // 36 //
37 // Author(s): nickg 37 // Author(s): nickg
38 // Contributors: nickg 38 // Contributors:nickg, jskov, hmt
39 // Date: 1998-02-17 39 // Date: 1998-02-17
40 // Purpose: Cache control API 40 // Purpose: Cache control API
41 // Description: The macros defined here provide the HAL APIs for handling 41 // Description: The macros defined here provide the HAL APIs for handling
42 // cache control operations. 42 // cache control operations.
43 // Usage: 43 // Usage:
52 #include <pkgconf/hal.h> 52 #include <pkgconf/hal.h>
53 #include <cyg/infra/cyg_type.h> 53 #include <cyg/infra/cyg_type.h>
54 54
55 #include <cyg/hal/ppc_regs.h> 55 #include <cyg/hal/ppc_regs.h>
56 56
57 #include <cyg/hal/plf_cache.h> 57 #include <cyg/hal/var_cache.h>
58 58
59 59
60 //============================================================================= 60 //=============================================================================
61 // Memory mapping 61 // Memory mapping
62 typedef struct { 62 typedef struct {
219 219
220 // Invalidate cache lines in the given range without writing to memory. 220 // Invalidate cache lines in the given range without writing to memory.
221 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) 221 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
222 222
223 223
224 //=============================================================================
225 // Motorola MPC8xx
226
227 #elif defined(CYGPKG_HAL_POWERPC_MPC8xx)
228
229 //-----------------------------------------------------------------------------
230 // Cache dimensions
231
232 #if defined(CYGPKG_HAL_POWERPC_MPC860)
233 // Data cache
234 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
235 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
236 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
237
238 // Instruction cache
239 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
240 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
241 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
242 #endif // defined(CYGPKG_HAL_POWERPC_MPC860)
243
244 #if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
245 // Data cache
246 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
247 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
248 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
249
250 // Instruction cache
251 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes
252 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
253 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
254 #endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
255
256 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
257 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
258
259 //-----------------------------------------------------------------------------
260 // Global control of data cache
261
262 // Enable the data cache
263 #define HAL_DCACHE_ENABLE() \
264 asm volatile ("sync;" \
265 "mtspr %0, %1;" \
266 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))
267
268 // Disable the data cache
269 #define HAL_DCACHE_DISABLE() \
270 asm volatile ("sync;" \
271 "mtspr %0, %1;" \
272 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))
273
274 // Invalidate the entire cache
275 // Note: Any locked lines will not be invalidated.
276 #define HAL_DCACHE_INVALIDATE_ALL() \
277 asm volatile ("sync;" \
278 "mtspr %0, %1;" \
279 : : "I" (CYGARC_REG_DC_CST), \
280 "r" (CYGARC_REG_DC_CMD_IA))
281
282 // Synchronize the contents of the cache with memory.
283 #define HAL_DCACHE_SYNC() \
284 CYG_MACRO_START \
285 cyg_int32 i; \
286 for (i = 0; i < HAL_DCACHE_SETS; i++){ \
287 asm volatile ("sync;" \
288 "mtspr %0, %2;" \
289 "mtspr %1, %4;" \
290 "mtspr %0, %3;" \
291 "mtspr %1, %4;" \
292 : /* no output */ \
293 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \
294 /* %1 */ "I" (CYGARC_REG_DC_CST), \
295 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
296 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
297 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \
298 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
299 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \
300 } \
301 CYG_MACRO_END
302
303 // Query the state of the data cache
304 #define HAL_DCACHE_IS_ENABLED(_state_) \
305 asm volatile ("mfspr %0, %1;" \
306 "rlwinm %0,%0,1,31,31;" \
307 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST))
308
309 // Set the data cache refill burst size
310 //#define HAL_DCACHE_BURST_SIZE(_size_)
311
312 // Set the data cache write mode
313 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
314
315 //#define HAL_DCACHE_WRITETHRU_MODE 0
316 //#define HAL_DCACHE_WRITEBACK_MODE 1
317
318
319 // Load the contents of the given address range into the data cache
320 // and then lock the cache so that it stays there.
321
322 // Restrictions: This implementation only allows a single area to be
323 // locked at any one time. This area must be 2kB or less in size.
324
325 // Implementation: Flush entire cache, then invalidate it. This
326 // ensures that the fetched data go into way0.
327
328 #define HAL_DCACHE_LOCK(_base_, _size_) \
329 CYG_MACRO_START \
330 cyg_int32 __scratch; \
331 cyg_uint32 __base = (cyg_uint32)(_base_); \
332 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \
333 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \
334 HAL_DCACHE_DISABLE(); \
335 HAL_DCACHE_SYNC (); \
336 HAL_DCACHE_INVALIDATE_ALL (); \
337 HAL_DCACHE_ENABLE(); \
338 do { \
339 asm volatile ("lbz %0,0(%1);" \
340 "sync;" \
341 "mtspr %2, %4;" \
342 "mtspr %3, %5;" \
343 : /* %0 */ "=&r" (__scratch) \
344 : /* %1 */ "b" (__base), \
345 /* %2 */ "I" (CYGARC_REG_DC_ADR), \
346 /* %3 */ "I" (CYGARC_REG_DC_CST), \
347 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
348 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
349 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \
350 __l++; \
351 __base += HAL_DCACHE_LINE_SIZE; \
352 } while (__count--); \
353 CYG_MACRO_END
354
355
356 // Undo a previous lock operation
357
358 // Implementation: Unlocks entire cache.
359
360 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
361 HAL_DCACHE_UNLOCK_ALL()
362
363
364 // Unlock entire cache
365 #define HAL_DCACHE_UNLOCK_ALL() \
366 CYG_MACRO_START \
367 asm volatile ("sync;" \
368 "mtspr %0, %1;" \
369 : : "I" (CYGARC_REG_DC_CST), \
370 "r" (CYGARC_REG_DC_CMD_UA)); \
371 CYG_MACRO_END
372
373
374
375 //-----------------------------------------------------------------------------
376 // Data cache line control
377
378 // Allocate cache lines for the given address range without reading its
379 // contents from memory.
380 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
381
382 // Write dirty cache lines to memory and invalidate the cache entries
383 // for the given address range.
384 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
385 CYG_MACRO_START \
386 cyg_uint32 __base = (cyg_uint32) (_base_); \
387 cyg_int32 __size = (cyg_int32) (_size_); \
388 while (__size > 0) { \
389 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
390 __base += HAL_DCACHE_LINE_SIZE; \
391 __size -= HAL_DCACHE_LINE_SIZE; \
392 } \
393 CYG_MACRO_END
394
395 // Invalidate cache lines in the given range without writing to memory.
396 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
397 CYG_MACRO_START \
398 cyg_uint32 __base = (cyg_uint32) (_base_); \
399 cyg_int32 __size = (cyg_int32) (_size_); \
400 while (__size > 0) { \
401 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
402 __base += HAL_DCACHE_LINE_SIZE; \
403 __size -= HAL_DCACHE_LINE_SIZE; \
404 } \
405 CYG_MACRO_END
406
407 // Write dirty cache lines to memory for the given address range.
408 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
409 CYG_MACRO_START \
410 cyg_uint32 __base = (cyg_uint32) (_base_); \
411 cyg_int32 __size = (cyg_int32) (_size_); \
412 while (__size > 0) { \
413 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
414 __base += HAL_DCACHE_LINE_SIZE; \
415 __size -= HAL_DCACHE_LINE_SIZE; \
416 } \
417 CYG_MACRO_END
418
419 // Preread the given range into the cache with the intention of reading
420 // from it later.
421 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
422 CYG_MACRO_START \
423 cyg_uint32 __base = (cyg_uint32) (_base_); \
424 cyg_int32 __size = (cyg_int32) (_size_); \
425 while (__size > 0) { \
426 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
427 __base += HAL_DCACHE_LINE_SIZE; \
428 __size -= HAL_DCACHE_LINE_SIZE; \
429 } \
430 CYG_MACRO_END
431
432 // Preread the given range into the cache with the intention of writing
433 // to it later.
434 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
435 CYG_MACRO_START \
436 cyg_uint32 __base = (cyg_uint32) (_base_); \
437 cyg_int32 __size = (cyg_int32) (_size_); \
438 while (__size > 0) { \
439 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
440 __base += HAL_DCACHE_LINE_SIZE; \
441 __size -= HAL_DCACHE_LINE_SIZE; \
442 } \
443 CYG_MACRO_END
444
445 // Allocate and zero the cache lines associated with the given range.
446 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
447 CYG_MACRO_START \
448 cyg_uint32 __base = (cyg_uint32) (_base_); \
449 cyg_int32 __size = (cyg_int32) (_size_); \
450 while (__size > 0) { \
451 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
452 __base += HAL_DCACHE_LINE_SIZE; \
453 __size -= HAL_DCACHE_LINE_SIZE; \
454 } \
455 CYG_MACRO_END
456
457 //-----------------------------------------------------------------------------
458 // Global control of Instruction cache
459
460 // Enable the instruction cache
461 #define HAL_ICACHE_ENABLE() \
462 asm volatile ("isync;" \
463 "mtspr %0, %1;" \
464 "isync" \
465 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
466
467 // Disable the instruction cache
468 #define HAL_ICACHE_DISABLE() \
469 asm volatile ("isync;" \
470 "mtspr %0, %1;" \
471 "isync" \
472 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD))
473
474 // Invalidate the entire cache
475 #define HAL_ICACHE_INVALIDATE_ALL() \
476 asm volatile ("isync;" \
477 "mtspr %0, %1;" \
478 "isync" \
479 : : "I" (CYGARC_REG_IC_CST), \
480 "r" (CYGARC_REG_IC_CMD_IA))
481
482 // Synchronize the contents of the cache with memory.
483 #define HAL_ICACHE_SYNC() \
484 HAL_ICACHE_INVALIDATE_ALL()
485
486 // Query the state of the instruction cache
487 #define HAL_ICACHE_IS_ENABLED(_state_) \
488 asm volatile ("mfspr %0, %1;" \
489 "rlwinm %0,%0,1,31,31;" \
490 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST))
491
492 // Set the instruction cache refill burst size
493 //#define HAL_ICACHE_BURST_SIZE(_size_)
494
495
496 // Load the contents of the given address range into the instruction cache
497 // and then lock the cache so that it stays there.
498
499 // Restrictions: This implementation only allows a single area to be
500 // locked at any one time. This area must be 2kB or less in size.
501
502 // Implementation: Flush entire cache, then invalidate it. This
503 // ensures that the fetched data go into way0.
504
505 #define HAL_ICACHE_LOCK(_base_, _size_) \
506 CYG_MACRO_START \
507 unsigned long __base = \
508 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \
509 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \
510 do { \
511 asm volatile ("mtspr %0, %2;" \
512 "mtspr %1, %3;" \
513 "isync;" \
514 : /* no output */ \
515 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \
516 /* %1 */ "I" (CYGARC_REG_IC_CST), \
517 /* %2 */ "r" (__base), \
518 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \
519 __base += HAL_ICACHE_LINE_SIZE; \
520 } while (__count--); \
521 CYG_MACRO_END
522
523 // Undo a previous lock operation
524
525 // Implementation: Unlocks entire cache.
526 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
527 HAL_ICACHE_UNLOCK_ALL()
528
529 // Unlock entire cache
530 #define HAL_ICACHE_UNLOCK_ALL() \
531 CYG_MACRO_START \
532 asm volatile ("sync;" \
533 "mtspr %0, %1;" \
534 : : "I" (CYGARC_REG_IC_CST), \
535 "r" (CYGARC_REG_IC_CMD_UA)); \
536 CYG_MACRO_END
537
538 //-----------------------------------------------------------------------------
539 // Instruction cache line control
540
541 // Invalidate cache lines in the given range without writing to memory.
542 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
543
544 #endif 224 #endif
545 225
546 //----------------------------------------------------------------------------- 226 //-----------------------------------------------------------------------------
547 #endif // ifndef CYGONCE_HAL_CACHE_H 227 #endif // ifndef CYGONCE_HAL_CACHE_H
548 // End of hal_cache.h 228 // End of hal_cache.h