Mercurial > flash_v2
annotate packages/hal/powerpc/arch/current/include/hal_cache.h @ 70:c5536bad4c24 ecos-sw-2000-02-11
Merge from eCos master repository on 2000-02-11-15:46:40-GMT
| author | jlarmour |
|---|---|
| date | Fri, 11 Feb 2000 16:47:32 +0000 |
| parents | f74b2666b30d |
| children | da3908c9cd10 |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
12 // |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
13 // ------------------------------------------- |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
14 // The contents of this file are subject to the Red Hat eCos Public License |
|
66
bf00f99aec69
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
jlarmour
parents:
64
diff
changeset
|
15 // Version 1.1 (the "License"); you may not use this file except in |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
16 // compliance with the License. You may obtain a copy of the License at |
|
66
bf00f99aec69
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
jlarmour
parents:
64
diff
changeset
|
17 // http://www.redhat.com/ |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
18 // |
|
66
bf00f99aec69
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
jlarmour
parents:
64
diff
changeset
|
19 // Software distributed under the License is distributed on an "AS IS" |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
21 // License for the specific language governing rights and limitations under |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
22 // the License. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
23 // |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
24 // The Original Code is eCos - Embedded Configurable Operating System, |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
25 // released September 30, 1998. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
26 // |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
27 // The Initial Developer of the Original Code is Red Hat. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
28 // Portions created by Red Hat are |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
30 // All Rights Reserved. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
31 // ------------------------------------------- |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
32 // |
| 0 | 33 //####COPYRIGHTEND#### |
| 34 //============================================================================= | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 37 // Author(s): nickg | |
|
70
c5536bad4c24
Merge from eCos master repository on 2000-02-11-15:46:40-GMT
jlarmour
parents:
68
diff
changeset
|
38 // Contributors:nickg, jskov, hmt |
| 0 | 39 // Date: 1998-02-17 |
| 40 // Purpose: Cache control API | |
| 41 // Description: The macros defined here provide the HAL APIs for handling | |
| 42 // cache control operations. | |
| 43 // Usage: | |
| 44 // #include <cyg/hal/hal_cache.h> | |
| 45 // ... | |
| 46 // | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //============================================================================= | |
| 51 | |
| 52 #include <pkgconf/hal.h> | |
| 53 #include <cyg/infra/cyg_type.h> | |
| 2 | 54 |
| 0 | 55 #include <cyg/hal/ppc_regs.h> |
| 56 | |
|
70
c5536bad4c24
Merge from eCos master repository on 2000-02-11-15:46:40-GMT
jlarmour
parents:
68
diff
changeset
|
57 #include <cyg/hal/var_cache.h> |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
58 |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
59 |
| 0 | 60 //============================================================================= |
| 2 | 61 // Memory mapping |
| 62 typedef struct { | |
| 63 CYG_ADDRESS virtual_addr; | |
| 64 CYG_ADDRESS physical_addr; | |
| 65 cyg_int32 size; | |
| 66 cyg_uint8 flags; | |
| 67 } cyg_memdesc_t; | |
| 68 | |
|
16
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
69 // each platform HAL must provide one of these to describe how memory |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
70 // should be mapped/cached, ideally weak aliased so that apps can override: |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
71 externC cyg_memdesc_t cyg_hal_mem_map[]; |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
72 |
| 2 | 73 #define CYGARC_MEMDESC_CI 1 // cache inhibit |
| 74 #define CYGARC_MEMDESC_GUARDED 2 // guarded | |
| 75 | |
|
16
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
76 // these macros should ease that task, and ease any future extension of the |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
77 // structure (physical == virtual addresses): |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
78 #define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \ |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
79 { (_va_), (_va_), (_sz_), 0 } |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
80 |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
81 #define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \ |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
82 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI } |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
83 |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
84 #define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \ |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
85 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED } |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
86 |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
87 #define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \ |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
88 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI } |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
89 |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
90 #define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0} |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
91 #define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[] |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
92 #define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END } |
|
4f2df4ab82c8
Merge from eCos master repository on 1999-06-18-15:25:04-BST
jlarmour
parents:
10
diff
changeset
|
93 |
| 2 | 94 //============================================================================= |
| 0 | 95 // PowerPC simulator |
| 96 | |
|
68
f74b2666b30d
Merge from eCos master repository on 2000-02-04-07:47:04-GMT
jlarmour
parents:
66
diff
changeset
|
97 #ifdef CYGPKG_HAL_POWERPC_SIM |
| 0 | 98 |
| 99 //----------------------------------------------------------------------------- | |
| 100 // Cache dimensions | |
| 101 | |
| 102 // Data cache | |
| 103 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 104 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 105 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 106 | |
| 107 // Instruction cache | |
| 108 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 109 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 110 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 111 | |
| 112 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 113 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 114 | |
| 115 //----------------------------------------------------------------------------- | |
| 116 // Global control of data cache | |
| 117 | |
| 118 // Enable the data cache | |
| 119 #define HAL_DCACHE_ENABLE() | |
| 120 | |
| 121 // Disable the data cache | |
| 122 #define HAL_DCACHE_DISABLE() | |
| 123 | |
| 124 // Invalidate the entire cache | |
| 125 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 126 | |
| 127 // Synchronize the contents of the cache with memory. | |
| 128 #define HAL_DCACHE_SYNC() | |
| 129 | |
| 2 | 130 // Query the state of the data cache |
| 131 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 132 CYG_MACRO_START \ | |
| 133 (_state_) = 0; \ | |
| 134 CYG_MACRO_END | |
| 135 | |
| 0 | 136 // Set the data cache refill burst size |
| 137 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 138 | |
| 139 // Set the data cache write mode | |
| 140 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 141 | |
| 142 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 143 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 144 | |
| 145 // Load the contents of the given address range into the data cache | |
| 146 // and then lock the cache so that it stays there. | |
| 147 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 148 | |
| 149 // Undo a previous lock operation | |
| 150 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 151 | |
| 2 | 152 // Unlock entire cache |
| 153 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 154 | |
| 0 | 155 //----------------------------------------------------------------------------- |
| 156 // Data cache line control | |
| 157 | |
| 158 // Allocate cache lines for the given address range without reading its | |
| 159 // contents from memory. | |
| 160 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 161 | |
| 162 // Write dirty cache lines to memory and invalidate the cache entries | |
| 163 // for the given address range. | |
| 164 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 165 | |
| 166 // Invalidate cache lines in the given range without writing to memory. | |
| 167 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 168 | |
| 169 // Write dirty cache lines to memory for the given address range. | |
| 170 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 171 | |
| 172 // Preread the given range into the cache with the intention of reading | |
| 173 // from it later. | |
| 174 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 175 | |
| 176 // Preread the given range into the cache with the intention of writing | |
| 177 // to it later. | |
| 178 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 179 | |
| 180 // Allocate and zero the cache lines associated with the given range. | |
| 181 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 182 | |
| 183 //----------------------------------------------------------------------------- | |
| 184 // Global control of Instruction cache | |
| 185 | |
| 186 // Enable the instruction cache | |
| 187 #define HAL_ICACHE_ENABLE() | |
| 188 | |
| 189 // Disable the instruction cache | |
| 190 #define HAL_ICACHE_DISABLE() | |
| 191 | |
| 192 // Invalidate the entire cache | |
| 193 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 194 | |
| 195 // Synchronize the contents of the cache with memory. | |
| 196 #define HAL_ICACHE_SYNC() | |
| 197 | |
| 2 | 198 // Query the state of the instruction cache |
| 199 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 200 CYG_MACRO_START \ | |
| 201 (_state_) = 0; \ | |
| 202 CYG_MACRO_END | |
| 203 | |
| 0 | 204 // Set the instruction cache refill burst size |
| 205 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 206 | |
| 207 // Load the contents of the given address range into the instruction cache | |
| 208 // and then lock the cache so that it stays there. | |
| 209 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 210 | |
| 211 // Undo a previous lock operation | |
| 212 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 213 | |
| 2 | 214 // Unlock entire cache |
| 215 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 216 | |
| 0 | 217 //----------------------------------------------------------------------------- |
| 218 // Instruction cache line control | |
| 219 | |
| 220 // Invalidate cache lines in the given range without writing to memory. | |
| 221 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 222 | |
| 223 | |
| 224 #endif | |
| 225 | |
| 226 //----------------------------------------------------------------------------- | |
| 227 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 228 // End of hal_cache.h |