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comparison packages/hal/powerpc/arch/current/include/hal_cache.h @ 72:da3908c9cd10 ecos-sw-2000-02-17

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Merge from eCos master repository on 2000-02-17-18:56:14-GMT
author jlarmour
date Thu, 17 Feb 2000 19:38:13 +0000
parents c5536bad4c24
children e0c0827131d1
comparison
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71:f4a0d3a26b92 72:da3908c9cd10
54 54
55 #include <cyg/hal/ppc_regs.h> 55 #include <cyg/hal/ppc_regs.h>
56 56
57 #include <cyg/hal/var_cache.h> 57 #include <cyg/hal/var_cache.h>
58 58
59
60 //=============================================================================
61 // Memory mapping
62 typedef struct {
63 CYG_ADDRESS virtual_addr;
64 CYG_ADDRESS physical_addr;
65 cyg_int32 size;
66 cyg_uint8 flags;
67 } cyg_memdesc_t;
68
69 // each platform HAL must provide one of these to describe how memory
70 // should be mapped/cached, ideally weak aliased so that apps can override:
71 externC cyg_memdesc_t cyg_hal_mem_map[];
72
73 #define CYGARC_MEMDESC_CI 1 // cache inhibit
74 #define CYGARC_MEMDESC_GUARDED 2 // guarded
75
76 // these macros should ease that task, and ease any future extension of the
77 // structure (physical == virtual addresses):
78 #define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \
79 { (_va_), (_va_), (_sz_), 0 }
80
81 #define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \
82 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI }
83
84 #define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \
85 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED }
86
87 #define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \
88 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI }
89
90 #define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0}
91 #define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[]
92 #define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END }
93
94 //=============================================================================
95 // PowerPC simulator
96
97 #ifdef CYGPKG_HAL_POWERPC_SIM
98
99 //-----------------------------------------------------------------------------
100 // Cache dimensions
101
102 // Data cache
103 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
104 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
105 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
106
107 // Instruction cache
108 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
109 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
110 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
111
112 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
113 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
114
115 //-----------------------------------------------------------------------------
116 // Global control of data cache
117
118 // Enable the data cache
119 #define HAL_DCACHE_ENABLE()
120
121 // Disable the data cache
122 #define HAL_DCACHE_DISABLE()
123
124 // Invalidate the entire cache
125 #define HAL_DCACHE_INVALIDATE_ALL()
126
127 // Synchronize the contents of the cache with memory.
128 #define HAL_DCACHE_SYNC()
129
130 // Query the state of the data cache
131 #define HAL_DCACHE_IS_ENABLED(_state_) \
132 CYG_MACRO_START \
133 (_state_) = 0; \
134 CYG_MACRO_END
135
136 // Set the data cache refill burst size
137 //#define HAL_DCACHE_BURST_SIZE(_size_)
138
139 // Set the data cache write mode
140 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
141
142 //#define HAL_DCACHE_WRITETHRU_MODE 0
143 //#define HAL_DCACHE_WRITEBACK_MODE 1
144
145 // Load the contents of the given address range into the data cache
146 // and then lock the cache so that it stays there.
147 //#define HAL_DCACHE_LOCK(_base_, _size_)
148
149 // Undo a previous lock operation
150 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
151
152 // Unlock entire cache
153 //#define HAL_DCACHE_UNLOCK_ALL()
154
155 //-----------------------------------------------------------------------------
156 // Data cache line control
157
158 // Allocate cache lines for the given address range without reading its
159 // contents from memory.
160 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
161
162 // Write dirty cache lines to memory and invalidate the cache entries
163 // for the given address range.
164 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
165
166 // Invalidate cache lines in the given range without writing to memory.
167 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
168
169 // Write dirty cache lines to memory for the given address range.
170 //#define HAL_DCACHE_STORE( _base_ , _size_ )
171
172 // Preread the given range into the cache with the intention of reading
173 // from it later.
174 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
175
176 // Preread the given range into the cache with the intention of writing
177 // to it later.
178 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
179
180 // Allocate and zero the cache lines associated with the given range.
181 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
182
183 //-----------------------------------------------------------------------------
184 // Global control of Instruction cache
185
186 // Enable the instruction cache
187 #define HAL_ICACHE_ENABLE()
188
189 // Disable the instruction cache
190 #define HAL_ICACHE_DISABLE()
191
192 // Invalidate the entire cache
193 #define HAL_ICACHE_INVALIDATE_ALL()
194
195 // Synchronize the contents of the cache with memory.
196 #define HAL_ICACHE_SYNC()
197
198 // Query the state of the instruction cache
199 #define HAL_ICACHE_IS_ENABLED(_state_) \
200 CYG_MACRO_START \
201 (_state_) = 0; \
202 CYG_MACRO_END
203
204 // Set the instruction cache refill burst size
205 //#define HAL_ICACHE_BURST_SIZE(_size_)
206
207 // Load the contents of the given address range into the instruction cache
208 // and then lock the cache so that it stays there.
209 //#define HAL_ICACHE_LOCK(_base_, _size_)
210
211 // Undo a previous lock operation
212 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
213
214 // Unlock entire cache
215 //#define HAL_ICACHE_UNLOCK_ALL()
216
217 //-----------------------------------------------------------------------------
218 // Instruction cache line control
219
220 // Invalidate cache lines in the given range without writing to memory.
221 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
222
223
224 #endif
225
226 //----------------------------------------------------------------------------- 59 //-----------------------------------------------------------------------------
227 #endif // ifndef CYGONCE_HAL_CACHE_H 60 #endif // ifndef CYGONCE_HAL_CACHE_H
228 // End of hal_cache.h 61 // End of hal_cache.h