--- a/packages/hal/powerpc/arch/current/include/hal_cache.h
+++ b/packages/hal/powerpc/arch/current/include/hal_cache.h
@@ -56,173 +56,6 @@
 
 #include <cyg/hal/var_cache.h>
 
-
-//=============================================================================
-// Memory mapping
-typedef struct {
-    CYG_ADDRESS  virtual_addr;
-    CYG_ADDRESS  physical_addr;
-    cyg_int32    size;
-    cyg_uint8    flags;
-} cyg_memdesc_t;
-
-// each platform HAL must provide one of these to describe how memory
-// should be mapped/cached, ideally weak aliased so that apps can override:
-externC cyg_memdesc_t cyg_hal_mem_map[];
-
-#define CYGARC_MEMDESC_CI       1       // cache inhibit
-#define CYGARC_MEMDESC_GUARDED  2       // guarded
-
-// these macros should ease that task, and ease any future extension of the
-// structure (physical == virtual addresses):
-#define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \
-        { (_va_), (_va_), (_sz_), 0 }
-
-#define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \
-        { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI }
-
-#define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \
-        { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED }
-
-#define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \
-        { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI }
-
-#define CYGARC_MEMDESC_TABLE_END      {0, 0, 0, 0}
-#define CYGARC_MEMDESC_TABLE          cyg_memdesc_t cyg_hal_mem_map[]
-#define CYGARC_MEMDESC_EMPTY_TABLE    { CYGARC_MEMDESC_TABLE_END }
-
-//=============================================================================
-// PowerPC simulator
-
-#ifdef CYGPKG_HAL_POWERPC_SIM
-
-//-----------------------------------------------------------------------------
-// Cache dimensions
-
-// Data cache
-#define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
-#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
-#define HAL_DCACHE_WAYS                 2       // Associativity of the cache
-
-// Instruction cache
-#define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
-#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
-#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
-
-#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-
-//-----------------------------------------------------------------------------
-// Global control of data cache
-
-// Enable the data cache
-#define HAL_DCACHE_ENABLE()
-
-// Disable the data cache
-#define HAL_DCACHE_DISABLE()
-
-// Invalidate the entire cache
-#define HAL_DCACHE_INVALIDATE_ALL()
-
-// Synchronize the contents of the cache with memory.
-#define HAL_DCACHE_SYNC()
-
-// Query the state of the data cache
-#define HAL_DCACHE_IS_ENABLED(_state_)          \
-    CYG_MACRO_START                             \
-    (_state_) = 0;                              \
-    CYG_MACRO_END
-
-// Set the data cache refill burst size
-//#define HAL_DCACHE_BURST_SIZE(_size_)
-
-// Set the data cache write mode
-//#define HAL_DCACHE_WRITE_MODE( _mode_ )
-
-//#define HAL_DCACHE_WRITETHRU_MODE       0
-//#define HAL_DCACHE_WRITEBACK_MODE       1
-
-// Load the contents of the given address range into the data cache
-// and then lock the cache so that it stays there.
-//#define HAL_DCACHE_LOCK(_base_, _size_)
-
-// Undo a previous lock operation
-//#define HAL_DCACHE_UNLOCK(_base_, _size_)
-
-// Unlock entire cache
-//#define HAL_DCACHE_UNLOCK_ALL()
-
-//-----------------------------------------------------------------------------
-// Data cache line control
-
-// Allocate cache lines for the given address range without reading its
-// contents from memory.
-//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
-
-// Write dirty cache lines to memory and invalidate the cache entries
-// for the given address range.
-//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
-
-// Invalidate cache lines in the given range without writing to memory.
-//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
-
-// Write dirty cache lines to memory for the given address range.
-//#define HAL_DCACHE_STORE( _base_ , _size_ )
-
-// Preread the given range into the cache with the intention of reading
-// from it later.
-//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
-
-// Preread the given range into the cache with the intention of writing
-// to it later.
-//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
-
-// Allocate and zero the cache lines associated with the given range.
-//#define HAL_DCACHE_ZERO( _base_ , _size_ )
-
-//-----------------------------------------------------------------------------
-// Global control of Instruction cache
-
-// Enable the instruction cache
-#define HAL_ICACHE_ENABLE()
-
-// Disable the instruction cache
-#define HAL_ICACHE_DISABLE()
-
-// Invalidate the entire cache
-#define HAL_ICACHE_INVALIDATE_ALL()
-
-// Synchronize the contents of the cache with memory.
-#define HAL_ICACHE_SYNC()
-
-// Query the state of the instruction cache
-#define HAL_ICACHE_IS_ENABLED(_state_)          \
-    CYG_MACRO_START                             \
-    (_state_) = 0;                              \
-    CYG_MACRO_END
-
-// Set the instruction cache refill burst size
-//#define HAL_ICACHE_BURST_SIZE(_size_)
-
-// Load the contents of the given address range into the instruction cache
-// and then lock the cache so that it stays there.
-//#define HAL_ICACHE_LOCK(_base_, _size_)
-
-// Undo a previous lock operation
-//#define HAL_ICACHE_UNLOCK(_base_, _size_)
-
-// Unlock entire cache
-//#define HAL_ICACHE_UNLOCK_ALL()
-
-//-----------------------------------------------------------------------------
-// Instruction cache line control
-
-// Invalidate cache lines in the given range without writing to memory.
-//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
-
-
-#endif
-
 //-----------------------------------------------------------------------------
 #endif // ifndef CYGONCE_HAL_CACHE_H
 // End of hal_cache.h