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diff packages/hal/powerpc/arch/current/src/vectors.S @ 14:01ce82f3e11a ecos-sw-1999-06-11

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Merge from eCos master repository on 1999-06-11-17:05:41-BST
author jlarmour
date Fri, 11 Jun 1999 09:36:56 +0000
parents d3fbcdfa1b2f
children 4f2df4ab82c8
line wrap: on
line diff
--- a/packages/hal/powerpc/arch/current/src/vectors.S
+++ b/packages/hal/powerpc/arch/current/src/vectors.S
@@ -87,12 +87,13 @@ name:
 #define CYG_MSR CYG_MSR_COMMON
 #endif
 #ifdef CYG_HAL_POWERPC_SIM
-# When building for SIM, don't enable MMU -- it's not needed since caches
+# When building for SIM, don~t enable MMU -- it~s not needed since caches
 # are disabled, and there is a runtime simulation overhead.
 #undef CYG_MSR
 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR))
 #endif
 
+
 #===========================================================================
 # If the following option is enabled, we only save registers up to R12.
 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
@@ -283,9 +284,11 @@ 1:
         cmplw   r4,r5                   # compare
         blt     1b                      # loop if not yet done
 2:
+#endif
         
-#ifdef CYG_HAL_POWERPC_COPY_VECTORS
-        # Copy RAM exception vectors from ROM to RAM    
+        
+#ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for CygMon-supported startup
+        # Copy RAM exception vectors from ROM (or load place) to RAM
         lwi     r3,rom_vectors          # r3 = rom start
         lwi     r4,0                    # r4 = ram start
         lwi     r5,rom_vectors_end      # r5 = rom end
@@ -302,8 +305,6 @@ 1:
         blt     1b                      # loop if not yet done
 2:
 #endif
-        
-#endif
 
         # clear BSS
         .extern __bss_start
@@ -353,7 +354,7 @@ 2:
         sync
         mtmsr   r3
         sync
-
+	
         # Enable caches
         .extern hal_enable_caches
         bl      hal_enable_caches
@@ -367,6 +368,7 @@ 2:
         bl      initialize_stub
 #endif
 
+	
         .extern cyg_start
         bl      cyg_start                       # call cyg_start
 9:      
@@ -939,11 +941,13 @@ hal_vsr_table:
         .section ".sdata","aw"
 #endif
 
+        .extern hal_default_decrementer_isr
         .extern hal_default_isr
 
         .globl  hal_interrupt_handlers
 hal_interrupt_handlers:
-        .rept   CYG_ISR_TABLE_SIZE
+        .long   hal_default_decrementer_isr
+        .rept   CYG_ISR_TABLE_SIZE-1
         .long   hal_default_isr
         .endr