Mercurial > flash_v2

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 14:01ce82f3e11a ecos-sw-1999-06-11

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Merge from eCos master repository on 1999-06-11-17:05:41-BST
author jlarmour
date Fri, 11 Jun 1999 09:36:56 +0000
parents d3fbcdfa1b2f
children 4f2df4ab82c8
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1 ##==========================================================================
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2 ##
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3 ## vectors.S
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4 ##
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5 ## PowerPC exception vectors
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6 ##
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7 ##==========================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Cygnus eCos Public License
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12 # Version 1.0 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://sourceware.cygnus.com/ecos
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Cygnus Operating System, released
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22 # September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Cygnus. Portions created
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25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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26 # -------------------------------------------
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27 #
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28 #####COPYRIGHTEND####
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29 ##==========================================================================
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30 #######DESCRIPTIONBEGIN####
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31 ##
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32 ## Author(s): nickg, jskov
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33 ## Contributors: nickg, jskov
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34 ## Date: 1999-02-20
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35 ## Purpose: PowerPC exception vectors
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36 ## Description: This file defines the code placed into the exception
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37 ## vectors. It also contains the first level default VSRs
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38 ## that save and restore state for both exceptions and
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39 ## interrupts.
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40 ##
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41 ######DESCRIPTIONEND####
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42 ##
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43 ##==========================================================================
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44
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45 #include <pkgconf/hal.h>
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46
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47 #ifdef CYGPKG_KERNEL
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48 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT
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49 #endif
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50
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51 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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52 #include "cyg/hal/ppc_regs.h"
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53 #include "cyg/hal/ppc.inc"
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54
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55 #define FUNC_START(name) \
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56 .type name,@function; \
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57 .globl name; \
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58 name:
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59
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60 #===========================================================================
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61
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62 .file "vectors.S"
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63
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64 .extern hal_interrupt_handlers
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65 .extern hal_interrupt_data
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66 .extern hal_interrupt_objects
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67
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68 .extern cyg_instrument
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69
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70 .extern hal_hardware_init
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71
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72 #===========================================================================
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73 # MSR initialization value
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74 # zero all bits except:
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75 # FP = floating point available
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76 # ME = machine check enabled
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77 # IP = vectors at 0xFFFxxxxx (ROM startup only)
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78 # IR = instruction address translation
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79 # DR = data address translation
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80 # RI = recoverable interrupt
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81
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82 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI)
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83 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS)
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84 #define CYG_MSR (CYG_MSR_COMMON | MSR_IP)
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85 #endif
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86 #ifdef CYG_HAL_STARTUP_RAM
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87 #define CYG_MSR CYG_MSR_COMMON
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88 #endif
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89 #ifdef CYG_HAL_POWERPC_SIM
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90 # When building for SIM, don~t enable MMU -- it~s not needed since caches
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91 # are disabled, and there is a runtime simulation overhead.
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92 #undef CYG_MSR
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93 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR))
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94 #endif
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95
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96
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97 #===========================================================================
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98 # If the following option is enabled, we only save registers up to R12.
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99 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
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100 # not need to save them when calling C functions.
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101
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102 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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103
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104 #define MAX_SAVE_REG 12
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105
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106 #else
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107
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108 #define MAX_SAVE_REG 31
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109
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110 #endif
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111
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112 #===========================================================================
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113 # Start by defining the exceptions vectors that must be placed at
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114 # locations 0xFFF00000 and 0x00000000. The following code will normally
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115 # be located at 0xFFF00000 in the ROM. It may optionally be copied out
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116 # to 0x00000000 if we want to use the RAM vectors. For this reason this code
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117 # MUST BE POSITION INDEPENDENT. In RAM loaded configurations, this code may
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118 # be placed at 0x00000000 during loading.
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119
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120 .section ".vectors","ax"
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121
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122 #---------------------------------------------------------------------------
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123 # Unused first vector.
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124
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125 rom_vectors:
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126 lwi r3,_start
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127 mtlr r3
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128 blr
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129
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130 .byte 0x11
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131 .byte 0x22
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132 .byte 0x33
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133 .byte 0x44
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134
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135 #---------------------------------------------------------------------------
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136 # Reset vector.
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137
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138 .p2align 8
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139 .globl reset_vector
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140
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141 reset_vector:
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142 lwi r3,_start
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143 mtlr r3
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144 blr
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145
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146 #---------------------------------------------------------------------------
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147 # Macro for generating an exception vector service routine
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148
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149 .macro exception_vector name
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150 .p2align 8
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151 .globl __exception_\name
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152 __exception_\name:
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153 mtspr SPRG1,r3 # stash some work registers away
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154 mtspr SPRG2,r4
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155 mtspr SPRG3,r5
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156 mfcr r4 # stash CR
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157 li r5,__exception_\name@L # load low half of vector address
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158 srwi r5,r5,6 # shift right by 6
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159 lwi r3,hal_vsr_table # table base
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160 lwzx r3,r3,r5 # address of vsr
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161 mflr r5 # save link register
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162 mtlr r3 # put vsr address into it
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163 li r3,__exception_\name@L # reload low half of vector address
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164 blr # go to common code
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165 .endm
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166
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167 #---------------------------------------------------------------------------
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168 # Define the exception vectors.
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169
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170 # These are the architecture defined vectors that
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171 # are always present.
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172
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173 exception_vector machine_check
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174 exception_vector data_storage
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175 exception_vector instruction_storage
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176 exception_vector external
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177 exception_vector alignment
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178 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) \
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179 || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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180 exception_vector program
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181 #else
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182 # Provide a crude hook to the GDB exception handler in ROM.
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183 # This allows the testing infrastructure to rely on breakpoints
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184 # to terminate tests, even when the tests are compiled without
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185 # the GDB stub.
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186 # It is _not_ a generic solution to the problem; in particular it
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187 # is not possible to continue after a breakpoint is hit.
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188 .p2align 8
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189 .globl __exception_program
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190 __exception_program:
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191 bl _init_CPU # disable caches.
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192 lwi r3,0xfff00700 # address of trap handler
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193 mtlr r3 # in ROM.
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194 blr # jump to it.
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195
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196 #endif
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197 exception_vector floatingpoint_unavailable
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198 exception_vector decrementer
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199 exception_vector reserved_00a00
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200 exception_vector reserved_00b00
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201 exception_vector system_call
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202 exception_vector trace
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203 exception_vector floatingpoint_assist
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204 exception_vector reserved_00f00
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205
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206 # There are some additional vectors defined
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207 # on various implementations.
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208
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209 #ifdef CYG_HAL_POWERPC_MPC8xx
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210 # MPC8xx vectors
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211
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212 exception_vector software_emu
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213 exception_vector instruction_tlb_miss
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214 exception_vector data_tlb_miss
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215 exception_vector instruction_tlb_error
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216 exception_vector data_tlb_error
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217 exception_vector reserved_01500
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218 exception_vector reserved_01600
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219 exception_vector reserved_01700
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220 exception_vector reserved_01800
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221 exception_vector reserved_01900
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222 exception_vector reserved_01A00
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223 exception_vector reserved_01B00
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224 exception_vector data_breakpoint
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225 exception_vector instruction_breakpoint
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226 exception_vector peripheral_breakpoint
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227 exception_vector NMI_port
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228
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229 #endif
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230 rom_vectors_end:
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231
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232 #===========================================================================
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233 # Real startup code. We jump here from the various reset vectors to set up
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234 # the world.
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235
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236 .text
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237 .globl _start
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238
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239 _start:
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240 # Initialize CPU
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241 bl _init_CPU
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242
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243 #ifdef CYG_HAL_POWERPC_MPC8xx
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244 # Disable special MPC8xx "development support" which
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245 # suppresses trace exceptions. The CPU seems to hang, not
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246 # executing from offset 0x1e00(?) as expected.
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247 li r3,0
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248 mtspr DER, r3
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249 #endif
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250
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251 # Set up global offset table
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252 lwi r2,_GLOBAL_OFFSET_TABLE_
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253
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254 # set up time base register to zero
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255 xor r3,r3,r3
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256 mtspr TBL_W,r3
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257 xor r4,r4,r4
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258 mtspr TBU_W,r4
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259
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260 # Call platform specific hardware initialization
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261 # This may include memory controller initialization. It is not
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262 # safe to access RAM until after this point.
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263 bl hal_hardware_init
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264
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265 # set up stack
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266 lwi sp,__interrupt_stack
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267 mtspr SPRG0,sp # save in sprg0 for later use
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268
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269 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS)
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270
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271 # Copy data from ROM to ram
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272 lwi r3,__rom_data_start # r3 = rom start
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273 lwi r4,__ram_data_start # r4 = ram start
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274 lwi r5,__ram_data_end # r5 = ram end
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275
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276 cmplw r4,r5 # skip if no data
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277 beq 2f
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278
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279 1:
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280 lwz r0,0(r3) # get word from ROM
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281 stw r0,0(r4) # store in RAM
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282 addi r3,r3,4 # increment by 1 word
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283 addi r4,r4,4 # increment by 1 word
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284 cmplw r4,r5 # compare
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285 blt 1b # loop if not yet done
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286 2:
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287 #endif
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288
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289
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290 #ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for CygMon-supported startup
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291 # Copy RAM exception vectors from ROM (or load place) to RAM
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292 lwi r3,rom_vectors # r3 = rom start
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293 lwi r4,0 # r4 = ram start
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294 lwi r5,rom_vectors_end # r5 = rom end
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295
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296 cmplw r3,r5 # skip if no vectors
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297 beq 2f
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298
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299 1:
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300 lwz r0,0(r3) # get word from ROM
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301 stw r0,0(r4) # store in RAM
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302 addi r3,r3,4 # increment by 1 word
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303 addi r4,r4,4 # increment by 1 word
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304 cmplw r3,r5 # compare
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305 blt 1b # loop if not yet done
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306 2:
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307 #endif
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308
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309 # clear BSS
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310 .extern __bss_start
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311 .extern __bss_end
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312 lwi r3,__bss_start # r3 = start
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313 lwi r4,__bss_end # r4 = end
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314 li r0,0 # r0 = 0
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315 cmplw r3,r4 # skip if no bss
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316 beq 2f
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317
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318 1: stw r0,0(r3) # store zero
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319 addi r3,r3,4 # increment by 1 word
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320 cmplw r3,r4 # compare
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321 blt 1b # loop if not yet done
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322 2:
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323
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324 # clear SBSS
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325 .extern __sbss_start
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326 .extern __sbss_end
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327 lwi r3,__sbss_start # r3 = start
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328 lwi r4,__sbss_end # r4 = end
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329 cmplw r3,r4 # skip if no sbss
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330 beq 2f
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331
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332 1: stw r0,0(r3) # store zero
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333 addi r3,r3,4 # increment by 1 word
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334 cmplw r3,r4 # compare
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335 blt 1b # loop if not yet done
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336 2:
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337
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338 # It is now safe to call C functions which may rely on initialized
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339 # data.
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340
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341 # Set up stack for calls to C code.
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342 subi sp,sp,12 # make space on stack
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343 li r0,0
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344 stw r0,0(sp) # clear back chain
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345 stw r0,8(sp) # zero return pc
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346 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
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347
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348 # Initialize MMU.
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349 .extern hal_MMU_init
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350 bl hal_MMU_init
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351
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352 # Enable MMU it so we can safely enable caches.
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353 lwi r3,CYG_MSR
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354 sync
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355 mtmsr r3
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356 sync
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357
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358 # Enable caches
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359 .extern hal_enable_caches
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360 bl hal_enable_caches
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361
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362 # call c++ constructors
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363 .extern cyg_hal_invoke_constructors
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364 bl cyg_hal_invoke_constructors
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365
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366 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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367 .extern initialize_stub
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368 bl initialize_stub
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369 #endif
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370
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01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST
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371
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372 .extern cyg_start
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373 bl cyg_start # call cyg_start
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374 9:
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375 b 9b # if we return, loop
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376
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377 #---------------------------------------------------------------------------
0
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378 # This code handles the common part of all exception handlers.
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379 # It saves the machine state onto the stack and then calls
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380 # a "C" routine to do the rest of the work. This work may result
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381 # in thread switches, and changes to the saved state. When we return
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382 # here the saved state is restored and execution is continued.
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383
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384 .text
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385
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386 .extern __default_exception_vsr
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387 __default_exception_vsr:
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388
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389 # We come here with all register containing their
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390 # pre-exception values except:
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391 # R3 = ls 16 bits of vector address
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392 # R4 = saved CR
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393 # R5 = saved LR
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394 # LR = VSR address
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395 # SPRG1 = old R3
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396 # SPRG2 = old R4
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397 # SPRG3 = old R5
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398 # SRR0 = old PC
2
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399 # SRR1 = old MSR and the exception cause (the POW state is lost!)
0
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400
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401 subi r1,r1,ppc_exception_decrement
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402 # leave space for registers and
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403 # a safety margin
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404
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405 # First, save away some registers
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406 stw r3,ppcreg_vector(r1) # stash vector
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407 stw r4,ppcreg_cr(r1) # stash CR
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408 stw r5,ppcreg_lr(r1) # stash LR
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409
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410 # Enable MMU.
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411 lwi r3,CYG_MSR
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412 sync
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413 mtmsr r3
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414 sync
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415
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416 mfspr r3,SPRG1 # save original R3
0
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417 stw r3,ppcreg_regs+3*4(r1)
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418 mfspr r4,SPRG2 # save original R4
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419 stw r4,ppcreg_regs+4*4(r1)
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420 mfspr r5,SPRG3 # save original R5
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421 stw r5,ppcreg_regs+5*4(r1)
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422
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423 stw r0,ppcreg_regs(r1) # save R0
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424 stw r2,ppcreg_regs+2*4(r1) # save R2
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425
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426 mr r3,r1 # recreate original R1
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427 addi r3,r3,ppc_exception_decrement
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428 stw r3,ppcreg_regs+1*4(r1) # and save it in state
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429
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430 # Save registers r6..r12/r31
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431 .set _reg,6
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432 .rept MAX_SAVE_REG+1-6
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433 stw _reg,(ppcreg_regs+_reg*4)(r1)
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434 .set _reg,_reg+1
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435 .endr
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436
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437 # Save registers used in vsr (r14+r15)
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438 stw r14,(ppcreg_regs+14*4)(r1)
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439 stw r15,(ppcreg_regs+15*4)(r1)
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440
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441 # get remaining CPU registers
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442 mfxer r3
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443 mfctr r5
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444 mfdar r6
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445 mfdsisr r7
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446 mfpvr r8
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447 mfsrr0 r9
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448 mfsrr1 r10
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449
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450 # and store them
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451 stw r3,ppcreg_xer(r1)
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452 stw r5,ppcreg_ctr(r1)
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453 stw r6,ppcreg_dar(r1)
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454 stw r7,ppcreg_dsisr(r1)
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455 stw r8,ppcreg_pvr(r1)
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456 stw r9,ppcreg_pc(r1)
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457 stw r10,ppcreg_msr(r1)
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458
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459 # The entire CPU state is now stashed on the stack,
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460 # call into C to do something with it.
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461
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462 mr r3,sp # R3 = register dump
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463
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464 subi sp,sp,ppc_stack_frame_size # make a null frame
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465
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466 li r0,0 # R0 = 0
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467 stw r0,0(sp) # backchain = 0
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468 stw r0,8(sp) # return pc = 0
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469
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470 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
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471 # where C code can save LR
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472
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473 lwi r5,restore_state # get return link
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474 mtlr r5 # to link register
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475
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476 .extern cyg_hal_exception_handler
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477 b cyg_hal_exception_handler # call C code, r3 = registers
0
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478
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479 # When the call returns it will go to restore_state below.
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480
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481
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482 ##--------------------------------------------------------------------------
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483 ## The following macros are defined depending on whether the Interrupt
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484 ## system is using isr tables or chaining, and depending on the interrupt
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485 ## controller in the system.
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486
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487 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h.
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488
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489 #ifdef CYG_HAL_POWERPC_MPC8xx
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490
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491 ## First level decoding of MPC8xx SIU interrupt controller.
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492
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493 #define CYG_ISR_TABLE_SIZE 59
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494
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495 # decode the interrupt
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496 .macro decode_interrupt dreg,state
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497 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
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498 rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
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499 beq 0f # done if decrementer (vec 0)
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500 lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU
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501 lbz \dreg,0(\dreg) # vector.
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502 srwi \dreg,\dreg,2
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503 addi \dreg,\dreg,1 # Skip decrementer vector
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504 0: stw \dreg,ppcreg_vector(\state) # update vector in state frame.
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505 slwi \dreg,\dreg,2 # convert to byte offset.
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506 .endm
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507
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508 #else
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509
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510 ## This is the simple version. No interrupt controller, ppcreg_vector
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511 ## is updated with the decoded interrupt vector. Isr tables/chaining
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512 ## use same interrupt decoder.
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513 ## Bit 21 biffers between decrementer (0) and external (1).
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514
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515 #define CYG_ISR_TABLE_SIZE 2
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516
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517 # decode the interrupt
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518 .macro decode_interrupt dreg,state
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519 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
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520 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update
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521 stw \dreg,ppcreg_vector(\state) # vector in state frame.
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522 slwi \dreg,\dreg,2 # convert to word offset.
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523 .endm
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524
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525 #endif
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526
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527 #---------------------------------------------------------------------------
0
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528 # Common interrupt handling code.
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529
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530 .extern __default_interrupt_vsr
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531 __default_interrupt_vsr:
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532
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533 # We come here with all register containing their
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534 # pre-exception values except:
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535 # R3 = ls 16 bits of vector address
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536 # R4 = saved CR
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537 # R5 = saved LR
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538 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
539 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
540 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
541 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
542 # SRR0 = old PC
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
543 # SRR1 = old MSR
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
544
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
545
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
546 subi r1,r1,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
547 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
548 # a safety margin
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
549
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
550 stw r3,ppcreg_vector(r1) # stash vector
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
551 stw r4,ppcreg_cr(r1) # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
552 stw r5,ppcreg_lr(r1) # stash LR
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
553
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
554 # Enable MMU.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
555 lwi r3,CYG_MSR
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
556 sync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
557 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
558 sync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
559
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
560 mfspr r3,SPRG1 # save original R3
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
561 stw r3,ppcreg_regs+3*4(r1)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
562 mfspr r4,SPRG2 # save original R4
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
563 stw r4,ppcreg_regs+4*4(r1)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
564 mfspr r5,SPRG3 # save original R5
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
565 stw r5,ppcreg_regs+5*4(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
566
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
567 stw r0,ppcreg_regs(r1) # save R0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
568 stw r2,ppcreg_regs+2*4(r1) # save R2
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
569
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
570 mr r3,r1 # recreate original R1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
571 addi r3,r3,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
572 stw r3,ppcreg_regs+1*4(r1) # and save it in state
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
573
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
574 # Save registers r6..r12/r31
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
575 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
576 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
577 stw _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
578 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
579 .endr
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
580
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
581 # Save registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
582 stw r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
583 stw r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
584
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
585 # get remaining CPU registers
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
586 mfxer r3
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
587 mfctr r5
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
588 mfsrr0 r6
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
589 mfsrr1 r7
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
590
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
591 # and store them
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
592 stw r3,ppcreg_xer(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
593 stw r5,ppcreg_ctr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
594 stw r6,ppcreg_pc(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
595 stw r7,ppcreg_msr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
596
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
597 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
598 # increment the scheduler lock and call the ISR
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
599 # for this vector.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
600
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
601 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
602 .extern cyg_scheduler_sched_lock
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
603 lwi r3,cyg_scheduler_sched_lock
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
604 lwz r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
605 addi r4,r4,1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
606 stw r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
607 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
608
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
609 mr r14,sp # r14 = register dump
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
610
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
611 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
612 lwi r3,__interrupt_stack # stack top
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
613 lwi r4,__interrupt_stack_base # stack base
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
614 sub. r5,sp,r4 # sp - base
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
615 blt 1f # if < 0 - not on istack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
616 sub. r5,r3,sp # top - sp
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
617 bgt 2f # if > 0 - already on istack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
618
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
619 1: mr sp,r3 # switch to istack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
620
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
621 2: stwu r14,-4(sp) # save old SP on stack
0
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
622
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
623 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
624
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
625 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
626
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
627 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
628 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
629 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
630
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
631 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
632 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
633
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
634 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
635
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
636 lwi r3,0x0301 # r3 = type = INTR,RAISE
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
637 lwz r4,ppcreg_vector(r14) # arg1 = vector address
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
638 srwi r4,r4,8 # arg1 = vector number
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
639 xor r5,r5,r5 # arg2 = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
640 bl cyg_instrument # call instrument function
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
641
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
642 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
643
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
644 decode_interrupt r15,r14 # get table index
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
645
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
646 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
647 .extern cyg_hal_gdb_isr
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
648 lwz r3,ppcreg_pc(r14) # for serial receive irq.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
649 bl cyg_hal_gdb_isr # (arg1 is PC)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
650 cmpwi r3,0x0000 # Call ISR proper?
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
651 beq 2f # (r3 is 0 when skipping
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
652 # to avoid DSR call)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
653 1:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
654 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
655
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
656 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
657
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
658 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
659 # The CPM controller allows nested interrupts. However,
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
660 # it sits on the back of the SIU controller which has no
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
661 # HW support for this. In effect, SW masking of lower
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
662 # priority IRQs in the SIU would be required for this to work.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
663 #endif
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
664
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
665 #endif
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
666
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
667 lwz r3,ppcreg_vector(r14) # retrieve decoded vector #
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
668
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
669 lwi r6,hal_interrupt_handlers # get interrupt handler table
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
670 lwzx r6,r6,r15 # load routine pointer
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
671
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
672 lwi r4,hal_interrupt_data # get interrupt data table
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
673 lwzx r4,r4,r15 # load data pointer
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
674 # R4 = data argument
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
675
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
676 mtctr r6 # put isr address in ctr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
677
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
678 bctrl # branch to ctr reg and link
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
679
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
680 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
681 # If interrupt was caused by GDB, the ISR call above
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
682 # is skipped by jumping here.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
683 2:
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
684 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
685
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
686 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
687
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
688 # If we are returning from the last nested interrupt, move back
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
689 # to the thread stack. interrupt_end() must be called on the
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
690 # thread stack since it potentially causes a context switch.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
691 # Since we have arranged for the top of stack location to
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
692 # contain the sp we need to go back to here, just pop it off
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
693 # and put it in SP.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
694
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
695
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
696 lwz sp,ppc_stack_frame_size*2(sp) # sp = *sp
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
697
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
698 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
699
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
700 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
701 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
702 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
703
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
704 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
705 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
706 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
707
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
708 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
709
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
710 # We only need to call _interrupt_end() when there is a kernel
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
711 # present to do any tidying up.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
712
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
713 # on return r3 bit 1 will indicate whether a DSR is
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
714 # to be posted. Pass this together with a pointer to
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
715 # the interrupt object we have just used to the
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
716 # interrupt tidy up routine.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
717
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
718 # Note that r14 and r15 are defined to be preserved across
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
719 # calls by the calling convention, so they still contain
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
720 # the register dump and the vector number respectively.
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
721
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
722 # Note: The instructions restoring the msr mask out the POW bit.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
723 # When eCos gets power management aware, this bit will have to be
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
724 # set to the correct state rather than just cleared.
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
725
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
726 lwi r4,hal_interrupt_objects # get interrupt object table
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
727 lwzx r4,r4,r15 # load object pointer
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
728
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
729 lwz r6,ppcreg_msr(r14) # restore msr, including
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
730 lis r5,0xfffe # interrupt enable.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
731 andc r6,r6,r5 # mask out reserved bits
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
732 sync # (and POW!)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
733 mtmsr r6
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
734 sync
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
735
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
736 mr r5,r14 # arg3 = saved register dump
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
737
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
738 .extern interrupt_end
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
739 bl interrupt_end # call into C to finish off
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
740 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
741
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
742 restore_state:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
743 # All done, restore CPU state and continue
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
744
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
745 addi sp,sp,ppc_stack_frame_size*2 # retrieve CPU state pointer
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
746
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
747 # get sprs we want to restore
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
748 lwz r3,ppcreg_cr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
749 lwz r4,ppcreg_pc(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
750 lwz r5,ppcreg_msr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
751 lwz r6,ppcreg_xer(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
752 lwz r7,ppcreg_lr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
753 lwz r8,ppcreg_ctr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
754
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
755
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
756 # stuff some of them into the CPU
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
757 mtxer r6
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
758 mtlr r7
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
759 mtctr r8
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
760
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
761 # restore R0 and R2
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
762 lwz r0,ppcreg_regs(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
763 lwz r2,ppcreg_regs+2*4(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
764
2
443894e2e912 Block commit of eCos version 1.2.1
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parents: 0
diff changeset
765 # Restore registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
766 lwz r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
767 lwz r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
768
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
769 # restore registers r6..r12/r31
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
770 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
771 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
772 lwz _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
773 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
774 .endr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
775
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
776 # Here all the registers are loaded except
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
777 # r1 = ppcregs
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
778 # r3 = ccr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
779 # r4 = srr0 = pc
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
780 # r5 = srr1 = msr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
781
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
782 # We have to disable interrupts while srr0 and
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
783 # srr1 are loaded, since another interrupt will
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
784 # destroy them.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
785
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
786 mtcr r3 # set ccr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
787
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
788 lwi r3,CYG_MSR # do rest with ints disabled
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
789 sync
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
790 mtmsr r3
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
791 sync
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
792
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
793 mtsrr0 r4 # load old pc
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
794 mtsrr1 r5 # load old msr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
795
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
796 lwz r3,ppcreg_regs+3*4(r1) # load r3 value
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
797 lwz r4,ppcreg_regs+4*4(r1) # load r4 value
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
798 lwz r5,ppcreg_regs+5*4(r1) # load r5 value
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
799 lwz r1,ppcreg_regs+1*4(r1) # restore r1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
800
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
801 sync # settle things down
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
802 isync
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
803 rfi # and return
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
804
10
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
805
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
806
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
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parents: 8
diff changeset
807 ##-----------------------------------------------------------------------------
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
808 ## Execute pending DSRs on the interrupt stack with interrupts enabled.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
809 ## Note: this can only be called from code running on a thread stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
810
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
811 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
812 .extern cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
813
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
814 FUNC_START(hal_interrupt_stack_call_pending_DSRs)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
815 # Disable interrupts
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
816 mfmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
817 lis r3,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
818 ori r3,r3,0x8000
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
819 andc r5,r4,r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
820 mtmsr r5
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
821
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
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diff changeset
822 # Change to interrupt stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
823 mr r3,sp
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
824 lwi sp,__interrupt_stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
825 stwu r3,-4(sp) # store old stackptr on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
826 mflr r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
827 stwu r3,-4(sp) # store lr on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
828 stwu r4,-4(sp) # store msr values on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
829 stwu r5,-4(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
830
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
831 # Set up stack for calls to C code.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
832 subi sp,sp,12 # make space on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
833 li r0,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
834 stw r0,0(sp) # clear back chain
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
835 stw r0,8(sp) # zero return pc
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
836 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
837
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
838 # Restore interrupt state
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
839 mtmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
840
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
841 # Call into kernel which will execute DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
842 bl cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
843
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
844 # Unwind stack and get msr values
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
845 lwzu r5,12+ppc_stack_frame_size(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
846 lwz r4,4(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
847 lwz r3,8(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
848 mtlr r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
849
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
850 # Disable interrupts
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
851 mtmsr r5
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
852
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
853 # Restore original stack pointer, original interrupt state and return
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
854 lwz sp,12(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
855 mtmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
856
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
857 blr
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
858 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents: 8
diff changeset
859
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
860 #---------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
861 # Code for putting the CPU in a post-reset state; disabling MMU and caches.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
862 _init_CPU:
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
863 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
864 lwi r3,CYGARC_REG_DC_CMD_CD
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
865 sync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
866 mtspr CYGARC_REG_DC_CST,r3
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
867 lwi r3,CYGARC_REG_IC_CMD_CD
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
868 isync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
869 mtspr CYGARC_REG_IC_CST,r3
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
870 isync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
871 #endif
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
872
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
873 # Set up MSR (disable MMU for now)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
874 lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
875 sync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
876 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
877 sync
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
878 blr
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879
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880 #---------------------------------------------------------------------------
0
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881 # This table contains a VSR pointer for each defined exception.
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882 # All of these except 5 and 9 point to the __default_exception_vsr
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883 # above, 5 and 9 point to the __default_interrupt_vsr. Entries in
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884 # this table may be changed using Cyg_Interrupt::set_vsr().
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885
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886 .data
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887
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888 .globl hal_vsr_table
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889 hal_vsr_table:
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890 # Architecture defined vectors
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891 .long __default_exception_vsr # reserved
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892 .long __default_exception_vsr # system reset
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893 .long __default_exception_vsr # machine check
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894 .long __default_exception_vsr # data storage
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895 .long __default_exception_vsr # instruction storage
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896
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897 .long __default_interrupt_vsr # external interrupt
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898
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899 .long __default_exception_vsr # alignment
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900 .long __default_exception_vsr # program
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901 .long __default_exception_vsr # floating point unavailable
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902
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903 .long __default_interrupt_vsr # decrementer
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904
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905 .long __default_exception_vsr # reserved 0x0a00
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906 .long __default_exception_vsr # reserved 0x0b00
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907 .long __default_exception_vsr # system call
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908 .long __default_exception_vsr # trace
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909 .long __default_exception_vsr # floating point assist
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910 .long __default_exception_vsr # reserved 0x0f00
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911
2
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912 #ifdef CYG_HAL_POWERPC_MPC8xx
0
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913
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914 # Implementation defined vectors
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915 .long __default_exception_vsr # software emulation
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916 .long __default_exception_vsr # instruction TLB miss
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917 .long __default_exception_vsr # data TLB miss
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918 .long __default_exception_vsr # instruction TLB error
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919 .long __default_exception_vsr # data TLB error
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920 .long __default_exception_vsr # reserved 0x1500
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921 .long __default_exception_vsr # reserved 0x1600
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922 .long __default_exception_vsr # reserved 0x1700
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923 .long __default_exception_vsr # reserved 0x1800
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924 .long __default_exception_vsr # reserved 0x1900
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925 .long __default_exception_vsr # reserved 0x1a00
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926 .long __default_exception_vsr # reserved 0x1b00
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927 .long __default_exception_vsr # data breakpoint
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928 .long __default_exception_vsr # instruction breakpoint
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929 .long __default_exception_vsr # peripheral breakpoint
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930 .long __default_exception_vsr # non maskable development port
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931 #endif
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932
2
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933 #---------------------------------------------------------------------------
0
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934 # Interrupt vector tables.
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935 # These tables contain the isr, data and object pointers used to deliver
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936 # interrupts to user code.
2
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937
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938 #if (CYG_ISR_TABLE_SIZE > 2)
0
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939 .data
2
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940 #else
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941 .section ".sdata","aw"
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942 #endif
0
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943
14
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944 .extern hal_default_decrementer_isr
0
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945 .extern hal_default_isr
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946
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947 .globl hal_interrupt_handlers
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948 hal_interrupt_handlers:
14
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949 .long hal_default_decrementer_isr
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950 .rept CYG_ISR_TABLE_SIZE-1
0
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951 .long hal_default_isr
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952 .endr
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953
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954 .globl hal_interrupt_data
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955 hal_interrupt_data:
2
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956 .rept CYG_ISR_TABLE_SIZE
0
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957 .long 0
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958 .endr
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959
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960 .globl hal_interrupt_objects
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961 hal_interrupt_objects:
2
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962 .rept CYG_ISR_TABLE_SIZE
0
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963 .long 0
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964 .endr
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965
2
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966 #---------------------------------------------------------------------------
0
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967 ## Temporary interrupt stack
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968
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969 .section ".bss"
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970
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971 .balign 16
8
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972 .global cyg_interrupt_stack_base
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973 cyg_interrupt_stack_base:
0
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974 __interrupt_stack_base:
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975 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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976 .byte 0
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977 .endr
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978 .balign 16
8
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979 .global cyg_interrupt_stack
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980 cyg_interrupt_stack:
0
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981 __interrupt_stack:
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982
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983 .long 0,0,0,0,0,0,0,0
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984
2
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985 #---------------------------------------------------------------------------
0
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986 # end of vectors.S