Mercurial > flash_v2
diff packages/hal/sh/sh4/current/include/variant.inc @ 1424:5268028c09c4
2003-09-21 Jonathan Larmour <jifl@eCosCentric.com>
* src/var_misc.c (hal_variant_init): Set FPSCR on startup.
* src/sh4_scif.c (cyg_hal_plf_scif_set_baud): New function, taken
from init code, but with fix to wait for hardware to settle.
(cyg_hal_plf_scif_control): Add __COMMCTL_GETBAUD and _SETBAUD support
using above function.
* include/sh4_scif.h: Add baud_rate to channel data.
* include/mod_regs_ser.h (CYGARC_SCBRR_N): Don't tweak BRR for
values < 4800 or > 115200 as it gets the values wrong. Instead trust
the developer to DTRT.
(CYGARC_REG_SCIF_SCLSR_ORER): Add definition for overrun in line status
reg.
2003-09-19 John Dallaway <jld@ecoscentric.com>
* cdl/hal_sh_sh4.cdl: Specify default CDL values for sh4_202_md
target.
2003-09-11 Nick Garnett <nickg@ecoscentric.com>
* include/var_regs.h (CYG_FPSCR): Changed initial value of fpscr
to do round-to-nearest rather than round-to-zero.
2003-09-08 Nick Garnett <nickg@ecoscentric.com>
* include/mod_202.h: Added define for UBC. The 202 appears to have
one, although there is no documented info. It is also not clear
what version it is. Setting this to 1 seems to work.
* include/mod_regs_cac.h:
* include/variant.inc:
Updated cache dimensions and initialization to support larger, two
way cache in sh4-202.
2003-09-05 Nick Garnett <nickg@ecoscentric.com>
* include/variant.inc:
* include/var_reg.h:
* include/mod_202.h:
* include/mod_regs_cpg.h:
* include/mod_regs_emi.h:
* include/mod_regs_femi.h:
* include/mod_regs_intc.h:
* cdl/hal_sh_sh4.cdl: Added SH-202 sub-variant, extra
functional units, and modifications to existing units for this
variant.
| author | nickg |
|---|---|
| date | Fri, 05 Dec 2003 17:07:29 +0000 |
| parents | d2c90368aeef |
| children |
line wrap: on
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--- a/packages/hal/sh/sh4/current/include/variant.inc +++ b/packages/hal/sh/sh4/current/include/variant.inc @@ -11,6 +11,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -43,7 +44,7 @@ #######DESCRIPTIONBEGIN#### ## ## Author(s): jskov -## Contributors:jskov +## Contributors:jskov, nickg ## Date: 2000-10-30 ## Purpose: SH4 variant definitions and init code ## Description: This file contains various definitions and macros that are @@ -77,15 +78,33 @@ #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) ##----------------------------------------------------------------------------- +## Cache control register initialization +## +## If we are starting from ROM, or are a RAM resident monitor, disable the cache +## initially. Otherwise we are a RAM loaded application, so keep the cache +## enabled. + +#if !defined(CYG_HAL_STARTUP_RAM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) +#define CYGARC_REG_CCR_INIT CYGARC_REG_CCR_EMODE +#else +#define CYGARC_REG_CCR_INIT (CYGARC_REG_CCR_CE|CYGARC_REG_CCR_EMODE) +#endif + +##----------------------------------------------------------------------------- ## Hardware init macros #ifndef CYGPKG_HAL_SH_POST_RESET_INIT .macro hal_post_reset_init # Initialize CPU mov.l $nCYG_SR,r1 ! Put CPU in a well-known state ldc r1,sr - mov #0,r0 + mov.l $nCYG_FPSCR,r1 + lds r1,fpscr + mov.l $nCYGARC_REG_CCR_INIT,r0 mov.l $nCYGARC_REG_CCR,r1 ! Disable cache mov.l r0,@r1 + mov #0,r0 mov.l $nCYGARC_REG_MMUCR,r1 ! Disable MMU mov.l r0,@r1 mov.l $nCYGARC_REG_BBRA,r1 ! Disable UBC Channel A @@ -129,8 +148,12 @@ .align 2 $nCYG_SR: .long CYG_SR +$nCYG_FPSCR: + .long CYG_FPSCR $nCYGARC_REG_CCR: .long CYGARC_REG_CCR +$nCYGARC_REG_CCR_INIT: + .long CYGARC_REG_CCR_INIT $nCYGARC_REG_MMUCR: .long CYGARC_REG_MMUCR $nCYGARC_REG_BBRA: